Remove stm32.
stm32 developemnt continues in the `stm32-neo` branch for now.
This commit is contained in:
Dario Nieuwenhuis
parent
97b01f1c47
commit
bfc7f52e6d
18
.github/workflows/rust.yml
vendored
18
.github/workflows/rust.yml
vendored
@ -55,24 +55,6 @@ jobs:
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- package: embassy-nrf
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target: thumbv7em-none-eabi
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features: nrf52840,defmt
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- package: embassy-stm32-examples
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target: thumbv7em-none-eabi
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features: stm32f405
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- package: embassy-stm32
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target: thumbv7em-none-eabi
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features: stm32f405
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- package: embassy-stm32
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target: thumbv7em-none-eabi
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features: stm32f446
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- package: embassy-stm32
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target: thumbv7em-none-eabi
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features: stm32f405,defmt
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- package: embassy-stm32
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target: thumbv6m-none-eabi
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features: stm32l0x2
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- package: embassy-stm32
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target: thumbv6m-none-eabi
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features: stm32l0x2,defmt
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- package: embassy-rp-examples
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target: thumbv6m-none-eabi
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@ -14,7 +14,6 @@ proc-macro2 = "1.0.24"
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proc-macro = true
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[features]
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stm32 = []
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nrf = []
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rp = []
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std = []
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@ -1,28 +0,0 @@
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use crate::path::ModulePrefix;
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use proc_macro2::TokenStream;
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use quote::quote;
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pub fn generate(embassy_prefix: &ModulePrefix, config: syn::Expr) -> TokenStream {
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let embassy_path = embassy_prefix.append("embassy").path();
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let embassy_stm32_path = embassy_prefix.append("embassy_stm32").path();
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quote!(
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use #embassy_stm32_path::{rtc, interrupt, Peripherals, pac, hal::rcc::RccExt, hal::time::U32Ext};
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unsafe { #embassy_stm32_path::system::configure(#config) };
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let (dp, clocks) = Peripherals::take().unwrap();
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let mut rtc = rtc::RTC::new(dp.TIM2, interrupt::take!(TIM2), clocks);
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let rtc = unsafe { make_static(&mut rtc) };
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rtc.start();
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let mut alarm = rtc.alarm1();
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unsafe { #embassy_path::time::set_clock(rtc) };
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let alarm = unsafe { make_static(&mut alarm) };
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executor.set_alarm(alarm);
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unsafe { Peripherals::set_peripherals(clocks) };
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)
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}
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@ -267,10 +267,6 @@ pub fn interrupt_take(item: TokenStream) -> TokenStream {
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#[path = "chip/nrf.rs"]
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mod chip;
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#[cfg(feature = "stm32")]
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#[path = "chip/stm32.rs"]
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mod chip;
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#[cfg(feature = "rp")]
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#[path = "chip/rp.rs"]
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mod chip;
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@ -284,7 +280,7 @@ struct MainArgs {
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config: Option<syn::LitStr>,
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}
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#[cfg(any(feature = "nrf", feature = "stm32", feature = "rp"))]
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#[cfg(any(feature = "nrf", feature = "rp"))]
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#[proc_macro_attribute]
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pub fn main(args: TokenStream, item: TokenStream) -> TokenStream {
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let macro_args = syn::parse_macro_input!(args as syn::AttributeArgs);
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@ -1,28 +0,0 @@
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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
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runner = "probe-run --chip STM32F401CCUx"
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rustflags = [
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# LLD (shipped with the Rust toolchain) is used as the default linker
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"-C", "link-arg=--nmagic",
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"-C", "link-arg=-Tlink.x",
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"-C", "link-arg=-Tdefmt.x",
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# if you run into problems with LLD switch to the GNU linker by commenting out
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# this line
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# "-C", "linker=arm-none-eabi-ld",
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# if you need to link to pre-compiled C libraries provided by a C toolchain
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# use GCC as the linker by commenting out both lines above and then
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# uncommenting the three lines below
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# "-C", "linker=arm-none-eabi-gcc",
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# "-C", "link-arg=-Wl,-Tlink.x",
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# "-C", "link-arg=-nostartfiles",
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# Code-size optimizations.
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"-Z", "trap-unreachable=no",
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"-C", "inline-threshold=5",
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"-C", "no-vectorize-loops",
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]
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[build]
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target = "thumbv7em-none-eabi"
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@ -1,53 +0,0 @@
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[package]
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authors = ["Dario Nieuwenhuis <dirbaio@dirbaio.net>"]
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edition = "2018"
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name = "embassy-stm32f4-examples"
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version = "0.1.0"
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[features]
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default = [
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"defmt-default",
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]
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defmt-default = []
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defmt-trace = []
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defmt-debug = []
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defmt-info = []
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defmt-warn = []
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defmt-error = []
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stm32f401 = ["embassy-stm32/stm32f401"]
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stm32f405 = ["embassy-stm32/stm32f405"]
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stm32f407 = ["embassy-stm32/stm32f407"]
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stm32f410 = ["embassy-stm32/stm32f410"]
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stm32f411 = ["embassy-stm32/stm32f411"]
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stm32f412 = ["embassy-stm32/stm32f412"]
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stm32f413 = ["embassy-stm32/stm32f413"]
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stm32f415 = ["embassy-stm32/stm32f405"]
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stm32f417 = ["embassy-stm32/stm32f407"]
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stm32f423 = ["embassy-stm32/stm32f413"]
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stm32f427 = ["embassy-stm32/stm32f427"]
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stm32f429 = ["embassy-stm32/stm32f429"]
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stm32f437 = ["embassy-stm32/stm32f427"]
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stm32f439 = ["embassy-stm32/stm32f429"]
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stm32f446 = ["embassy-stm32/stm32f446"]
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stm32f469 = ["embassy-stm32/stm32f469"]
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stm32f479 = ["embassy-stm32/stm32f469"]
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[dependencies]
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embassy = { version = "0.1.0", path = "../embassy", features = ["defmt", "defmt-trace"] }
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embassy-traits = { version = "0.1.0", path = "../embassy-traits", features = ["defmt"] }
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embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32" }
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embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
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defmt = "0.2.0"
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defmt-rtt = "0.2.0"
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cortex-m = "0.7.1"
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cortex-m-rt = "0.6.13"
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embedded-hal = { version = "0.2.4" }
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panic-probe = { version = "0.2.0", features = ["print-defmt"] }
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futures = { version = "0.3.8", default-features = false, features = ["async-await"] }
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rtt-target = { version = "0.3", features = ["cortex-m"] }
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bxcan = "0.5.0"
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usb-device = "0.2.7"
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@ -1,31 +0,0 @@
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//! This build script copies the `memory.x` file from the crate root into
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//! a directory where the linker can always find it at build time.
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//! For many projects this is optional, as the linker always searches the
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//! project root directory -- wherever `Cargo.toml` is. However, if you
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//! are using a workspace or have a more complicated build setup, this
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//! build script becomes required. Additionally, by requesting that
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//! Cargo re-run the build script whenever `memory.x` is changed,
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//! updating `memory.x` ensures a rebuild of the application with the
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//! new memory settings.
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use std::env;
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use std::fs::File;
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use std::io::Write;
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use std::path::PathBuf;
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fn main() {
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// Put `memory.x` in our output directory and ensure it's
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// on the linker search path.
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let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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File::create(out.join("memory.x"))
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.unwrap()
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.write_all(include_bytes!("memory.x"))
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.unwrap();
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println!("cargo:rustc-link-search={}", out.display());
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// By default, Cargo will re-run a build script whenever
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// any file in the project changes. By specifying `memory.x`
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// here, we ensure the build script is only re-run when
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// `memory.x` is changed.
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println!("cargo:rerun-if-changed=memory.x");
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}
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@ -1,5 +0,0 @@
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MEMORY
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{
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FLASH : ORIGIN = 0x08000000, LENGTH = 64K
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RAM : ORIGIN = 0x20000000, LENGTH = 32K
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}
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@ -1,57 +0,0 @@
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#![no_std]
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#![no_main]
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#![feature(trait_alias)]
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#![feature(type_alias_impl_trait)]
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#![feature(min_type_alias_impl_trait)]
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#![feature(impl_trait_in_bindings)]
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#[path = "../example_common.rs"]
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mod example_common;
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use example_common::{panic, *};
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use bxcan::filter::Mask32;
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use cortex_m_rt::entry;
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use embassy::executor::Executor;
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use embassy::util::Forever;
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use embassy_stm32::hal::prelude::*;
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use embassy_stm32::hal::{can::Can, stm32};
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use embassy_stm32::{can, interrupt};
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#[embassy::task]
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async fn run(dp: stm32::Peripherals, _cp: cortex_m::Peripherals) {
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let gpioa = dp.GPIOA.split();
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let rx = gpioa.pa11.into_alternate_af9();
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let tx = gpioa.pa12.into_alternate_af9();
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let mut can = bxcan::Can::new(Can::new(dp.CAN1, (tx, rx)));
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// APB1 (PCLK1): 24MHz, Bit rate: 20kBit/s, Sample Point 87.5%
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// Value was calculated with http://www.bittiming.can-wiki.info/
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can.modify_config().set_bit_timing(0x001c_004a);
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// Configure filters so that can frames can be received.
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can.modify_filters().enable_bank(0, Mask32::accept_all());
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let mut can = can::Can::new(can, interrupt::take!(CAN1_TX), interrupt::take!(CAN1_RX0));
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let _frame = can.receive().await;
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}
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static EXECUTOR: Forever<Executor> = Forever::new();
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#[entry]
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fn main() -> ! {
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let dp = stm32::Peripherals::take().unwrap();
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let cp = cortex_m::peripheral::Peripherals::take().unwrap();
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dp.DBGMCU.cr.modify(|_, w| {
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w.dbg_sleep().set_bit();
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w.dbg_standby().set_bit();
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w.dbg_stop().set_bit()
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});
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dp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled());
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let executor = EXECUTOR.put(Executor::new());
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executor.run(|spawner| {
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unwrap!(spawner.spawn(run(dp, cp)));
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});
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}
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@ -1,57 +0,0 @@
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#![no_std]
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#![no_main]
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#![feature(trait_alias)]
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#![feature(min_type_alias_impl_trait)]
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#![feature(impl_trait_in_bindings)]
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#![feature(type_alias_impl_trait)]
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#[path = "../example_common.rs"]
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mod example_common;
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use example_common::{panic, *};
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use cortex_m_rt::entry;
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use embassy::executor::Executor;
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use embassy::traits::gpio::*;
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use embassy::util::Forever;
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use embassy_stm32::exti::ExtiPin;
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use embassy_stm32::hal::prelude::*;
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use embassy_stm32::interrupt;
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use embassy_stm32::pac as stm32;
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use futures::pin_mut;
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#[embassy::task]
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async fn run(dp: stm32::Peripherals, _cp: cortex_m::Peripherals) {
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let gpioa = dp.GPIOA.split();
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let button = gpioa.pa0.into_pull_up_input();
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let mut syscfg = dp.SYSCFG.constrain();
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let mut pin = ExtiPin::new(button, interrupt::take!(EXTI0), &mut syscfg);
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info!("Starting loop");
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loop {
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pin.wait_for_rising_edge().await;
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info!("edge detected!");
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}
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}
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static EXECUTOR: Forever<Executor> = Forever::new();
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#[entry]
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fn main() -> ! {
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let dp = stm32::Peripherals::take().unwrap();
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let cp = cortex_m::peripheral::Peripherals::take().unwrap();
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dp.DBGMCU.cr.modify(|_, w| {
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w.dbg_sleep().set_bit();
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w.dbg_standby().set_bit();
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w.dbg_stop().set_bit()
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});
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dp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled());
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let executor = EXECUTOR.put(Executor::new());
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executor.run(|spawner| {
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unwrap!(spawner.spawn(run(dp, cp)));
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});
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}
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@ -1,42 +0,0 @@
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#![no_std]
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#![no_main]
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#![feature(trait_alias)]
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#![feature(min_type_alias_impl_trait)]
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#![feature(impl_trait_in_bindings)]
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#![feature(type_alias_impl_trait)]
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#[path = "../example_common.rs"]
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mod example_common;
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use example_common::*;
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use cortex_m_rt::entry;
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use embassy_stm32::hal::prelude::*;
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#[entry]
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fn main() -> ! {
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info!("Hello World!");
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let p = embassy_stm32::pac::Peripherals::take().unwrap();
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p.DBGMCU.cr.modify(|_, w| {
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w.dbg_sleep().set_bit();
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w.dbg_standby().set_bit();
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w.dbg_stop().set_bit()
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});
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p.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled());
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let gpioa = p.GPIOA.split();
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let gpioc = p.GPIOC.split();
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let mut led = gpioc.pc13.into_push_pull_output();
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let button = gpioa.pa0.into_pull_up_input();
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led.set_low().unwrap();
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loop {
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if button.is_high().unwrap() {
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led.set_low().unwrap();
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} else {
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led.set_high().unwrap();
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}
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}
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}
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@ -1,40 +0,0 @@
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#![no_std]
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#![no_main]
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#![feature(min_type_alias_impl_trait)]
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#![feature(impl_trait_in_bindings)]
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#![feature(type_alias_impl_trait)]
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#[path = "../example_common.rs"]
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mod example_common;
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use example_common::*;
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use defmt::panic;
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use embassy;
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use embassy::executor::Spawner;
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use embassy::time::{Duration, Timer};
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use embassy_stm32;
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use embassy_stm32::hal;
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#[embassy::task]
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async fn run1() {
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loop {
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info!("BIG INFREQUENT TICK");
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Timer::after(Duration::from_ticks(32768 * 2 as u64)).await;
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}
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}
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#[embassy::task]
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async fn run2() {
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loop {
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info!("tick");
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Timer::after(Duration::from_ticks(13000 as u64)).await;
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}
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}
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#[embassy::main(config = "embassy_stm32::system::Config::new().use_hse(16)")]
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async fn main(spawner: Spawner) {
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let (dp, clocks) = embassy_stm32::Peripherals::take().unwrap();
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spawner.spawn(run1()).unwrap();
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}
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@ -1,80 +0,0 @@
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#![no_std]
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#![no_main]
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#![feature(trait_alias)]
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#![feature(min_type_alias_impl_trait)]
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#![feature(impl_trait_in_bindings)]
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#![feature(type_alias_impl_trait)]
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#[path = "../example_common.rs"]
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mod example_common;
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use example_common::{panic, *};
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use cortex_m::singleton;
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use cortex_m_rt::entry;
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use embassy::executor::{Executor, Spawner};
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use embassy::traits::uart::{Read, ReadUntilIdle, Write};
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use embassy::util::Forever;
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use embassy_stm32::hal::dma::StreamsTuple;
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use embassy_stm32::hal::prelude::*;
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use embassy_stm32::hal::serial::config::Config;
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use embassy_stm32::interrupt;
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use embassy_stm32::pac as stm32;
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use embassy_stm32::serial;
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use futures::pin_mut;
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#[embassy::main(config = "embassy_stm32::system::Config::new().use_hse(16).sysclk(48).pclk1(24)")]
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async fn main(spawner: Spawner) {
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let (dp, clocks) = embassy_stm32::Peripherals::take().unwrap();
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let cp = cortex_m::peripheral::Peripherals::take().unwrap();
|
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dp.DBGMCU.cr.modify(|_, w| {
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w.dbg_sleep().set_bit();
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w.dbg_standby().set_bit();
|
||||
w.dbg_stop().set_bit()
|
||||
});
|
||||
|
||||
// https://gist.github.com/thalesfragoso/a07340c5df6eee3b04c42fdc69ecdcb1
|
||||
let gpioa = dp.GPIOA.split();
|
||||
let streams = StreamsTuple::new(dp.DMA2);
|
||||
|
||||
let _serial = unsafe {
|
||||
serial::Serial::new(
|
||||
dp.USART1,
|
||||
(streams.7, streams.2),
|
||||
(
|
||||
gpioa.pa9.into_alternate_af7(),
|
||||
gpioa.pa10.into_alternate_af7(),
|
||||
),
|
||||
interrupt::take!(DMA2_STREAM7),
|
||||
interrupt::take!(DMA2_STREAM2),
|
||||
interrupt::take!(USART1),
|
||||
Config::default().baudrate(9600.bps()),
|
||||
clocks,
|
||||
)
|
||||
};
|
||||
|
||||
let streams = StreamsTuple::new(dp.DMA1);
|
||||
|
||||
let mut serial = unsafe {
|
||||
serial::Serial::new(
|
||||
dp.USART2,
|
||||
(streams.6, streams.5),
|
||||
(
|
||||
gpioa.pa2.into_alternate_af7(),
|
||||
gpioa.pa3.into_alternate_af7(),
|
||||
),
|
||||
interrupt::take!(DMA1_STREAM6),
|
||||
interrupt::take!(DMA1_STREAM5),
|
||||
interrupt::take!(USART2),
|
||||
Config::default().baudrate(9600.bps()),
|
||||
clocks,
|
||||
)
|
||||
};
|
||||
pin_mut!(serial);
|
||||
|
||||
let buf = singleton!(: [u8; 30] = [0; 30]).unwrap();
|
||||
|
||||
buf[5] = 0x01;
|
||||
serial.as_mut().write(buf).await.unwrap();
|
||||
serial.as_mut().read_until_idle(buf).await.unwrap();
|
||||
}
|
||||
@ -1,119 +0,0 @@
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
#![feature(min_type_alias_impl_trait)]
|
||||
#![feature(impl_trait_in_bindings)]
|
||||
|
||||
#[path = "../example_common.rs"]
|
||||
mod example_common;
|
||||
use example_common::*;
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
use defmt::panic;
|
||||
use embassy::executor::{Executor, Spawner};
|
||||
use embassy::interrupt::InterruptExt;
|
||||
use embassy::io::{AsyncBufReadExt, AsyncWriteExt};
|
||||
use embassy::time::{Duration, Timer};
|
||||
use embassy::util::Forever;
|
||||
use embassy_extras::usb::usb_serial::UsbSerial;
|
||||
use embassy_extras::usb::Usb;
|
||||
use embassy_stm32::hal::otg_fs::{UsbBus, USB};
|
||||
use embassy_stm32::hal::prelude::*;
|
||||
use embassy_stm32::{interrupt, pac, rtc};
|
||||
use futures::future::{select, Either};
|
||||
use futures::pin_mut;
|
||||
use usb_device::bus::UsbBusAllocator;
|
||||
use usb_device::prelude::*;
|
||||
|
||||
#[embassy::task]
|
||||
async fn run1(bus: &'static mut UsbBusAllocator<UsbBus<USB>>) {
|
||||
info!("Async task");
|
||||
|
||||
let mut read_buf = [0u8; 128];
|
||||
let mut write_buf = [0u8; 128];
|
||||
let serial = UsbSerial::new(bus, &mut read_buf, &mut write_buf);
|
||||
|
||||
let device = UsbDeviceBuilder::new(bus, UsbVidPid(0x16c0, 0x27dd))
|
||||
.manufacturer("Fake company")
|
||||
.product("Serial port")
|
||||
.serial_number("TEST")
|
||||
.device_class(0x02)
|
||||
.build();
|
||||
|
||||
let irq = interrupt::take!(OTG_FS);
|
||||
irq.set_priority(interrupt::Priority::P3);
|
||||
|
||||
let usb = Usb::new(device, serial, irq);
|
||||
pin_mut!(usb);
|
||||
usb.as_mut().start();
|
||||
|
||||
let (mut read_interface, mut write_interface) = usb.as_ref().take_serial_0();
|
||||
|
||||
let mut buf = [0u8; 64];
|
||||
loop {
|
||||
let mut n = 0;
|
||||
let left = {
|
||||
let recv_fut = async {
|
||||
loop {
|
||||
let byte = unwrap!(read_interface.read_byte().await);
|
||||
unwrap!(write_interface.write_byte(byte).await);
|
||||
buf[n] = byte;
|
||||
|
||||
n += 1;
|
||||
if byte == b'\n' || byte == b'\r' || n == buf.len() {
|
||||
break;
|
||||
}
|
||||
}
|
||||
};
|
||||
pin_mut!(recv_fut);
|
||||
|
||||
let timeout = Timer::after(Duration::from_ticks(32768 * 10));
|
||||
|
||||
match select(recv_fut, timeout).await {
|
||||
Either::Left(_) => true,
|
||||
Either::Right(_) => false,
|
||||
}
|
||||
};
|
||||
|
||||
if left {
|
||||
for c in buf[..n].iter_mut() {
|
||||
if 0x61 <= *c && *c <= 0x7a {
|
||||
*c &= !0x20;
|
||||
}
|
||||
}
|
||||
unwrap!(write_interface.write_byte(b'\n').await);
|
||||
unwrap!(write_interface.write_all(&buf[..n]).await);
|
||||
unwrap!(write_interface.write_byte(b'\n').await);
|
||||
} else {
|
||||
unwrap!(write_interface.write_all(b"\r\nSend something\r\n").await);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static USB_BUS: Forever<UsbBusAllocator<UsbBus<USB>>> = Forever::new();
|
||||
|
||||
#[embassy::main(
|
||||
config = "embassy_stm32::system::Config::new().use_hse(25).sysclk(48).require_pll48clk()"
|
||||
)]
|
||||
async fn main(spawner: Spawner) -> ! {
|
||||
static mut EP_MEMORY: [u32; 1024] = [0; 1024];
|
||||
|
||||
info!("Hello World!");
|
||||
|
||||
let (p, clocks) = embassy_stm32::Peripherals::take().unwrap();
|
||||
|
||||
let gpioa = p.GPIOA.split();
|
||||
let usb = USB {
|
||||
usb_global: p.OTG_FS_GLOBAL,
|
||||
usb_device: p.OTG_FS_DEVICE,
|
||||
usb_pwrclk: p.OTG_FS_PWRCLK,
|
||||
pin_dm: gpioa.pa11.into_alternate_af10(),
|
||||
pin_dp: gpioa.pa12.into_alternate_af10(),
|
||||
hclk: clocks.hclk(),
|
||||
};
|
||||
// Rust analyzer isn't recognizing the static ref magic `cortex-m` does
|
||||
#[allow(unused_unsafe)]
|
||||
let usb_bus = USB_BUS.put(UsbBus::new(usb, unsafe { &mut EP_MEMORY }));
|
||||
|
||||
spawner.spawn(run1(usb_bus)).unwrap();
|
||||
}
|
||||
@ -1,17 +0,0 @@
|
||||
#![macro_use]
|
||||
|
||||
use defmt_rtt as _; // global logger
|
||||
use panic_probe as _;
|
||||
|
||||
pub use defmt::*;
|
||||
|
||||
use core::sync::atomic::{AtomicUsize, Ordering};
|
||||
|
||||
defmt::timestamp! {"{=u64}", {
|
||||
static COUNT: AtomicUsize = AtomicUsize::new(0);
|
||||
// NOTE(no-CAS) `timestamps` runs with interrupts disabled
|
||||
let n = COUNT.load(Ordering::Relaxed);
|
||||
COUNT.store(n + 1, Ordering::Relaxed);
|
||||
n as u64
|
||||
}
|
||||
}
|
||||
@ -1,53 +0,0 @@
|
||||
[package]
|
||||
name = "embassy-stm32"
|
||||
version = "0.1.0"
|
||||
authors = ["Dario Nieuwenhuis <dirbaio@dirbaio.net>"]
|
||||
edition = "2018"
|
||||
|
||||
[features]
|
||||
defmt-trace = [ ]
|
||||
defmt-debug = [ ]
|
||||
defmt-info = [ ]
|
||||
defmt-warn = [ ]
|
||||
defmt-error = [ ]
|
||||
|
||||
stm32f401 = ["stm32f4xx-hal/stm32f401"]
|
||||
stm32f405 = ["stm32f4xx-hal/stm32f405"]
|
||||
stm32f407 = ["stm32f4xx-hal/stm32f407"]
|
||||
stm32f410 = ["stm32f4xx-hal/stm32f410"]
|
||||
stm32f411 = ["stm32f4xx-hal/stm32f411"]
|
||||
stm32f412 = ["stm32f4xx-hal/stm32f412"]
|
||||
stm32f413 = ["stm32f4xx-hal/stm32f413"]
|
||||
stm32f415 = ["stm32f4xx-hal/stm32f405"]
|
||||
stm32f417 = ["stm32f4xx-hal/stm32f407"]
|
||||
stm32f423 = ["stm32f4xx-hal/stm32f413"]
|
||||
stm32f427 = ["stm32f4xx-hal/stm32f427"]
|
||||
stm32f429 = ["stm32f4xx-hal/stm32f429"]
|
||||
stm32f437 = ["stm32f4xx-hal/stm32f427"]
|
||||
stm32f439 = ["stm32f4xx-hal/stm32f429"]
|
||||
stm32f446 = ["stm32f4xx-hal/stm32f446"]
|
||||
stm32f469 = ["stm32f4xx-hal/stm32f469"]
|
||||
stm32f479 = ["stm32f4xx-hal/stm32f469"]
|
||||
|
||||
stm32l0x1 = ["stm32l0xx-hal/stm32l0x1"]
|
||||
stm32l0x2 = ["stm32l0xx-hal/stm32l0x2"]
|
||||
stm32l0x3 = ["stm32l0xx-hal/stm32l0x3"]
|
||||
|
||||
[dependencies]
|
||||
embassy = { version = "0.1.0", path = "../embassy" }
|
||||
embassy-macros = { version = "0.1.0", path = "../embassy-macros", features = ["stm32"]}
|
||||
embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
|
||||
|
||||
atomic-polyfill = "0.1.1"
|
||||
critical-section = "0.2.1"
|
||||
defmt = { version = "0.2.0", optional = true }
|
||||
log = { version = "0.4.11", optional = true }
|
||||
cortex-m-rt = "0.6.13"
|
||||
cortex-m = "0.7.1"
|
||||
embedded-hal = { version = "0.2.4" }
|
||||
embedded-dma = { version = "0.1.2" }
|
||||
bxcan = "0.5.0"
|
||||
nb = "*"
|
||||
stm32f4xx-hal = { version = "0.9.0", features = ["rt", "can", "usb_fs"], optional = true }
|
||||
stm32l0xx-hal = { version = "0.7.0", features = ["rt"], optional = true }
|
||||
futures = { version = "0.3.5", default-features = false, features = ["async-await"] }
|
||||
@ -1,120 +0,0 @@
|
||||
//! Async low power Serial.
|
||||
//!
|
||||
//! The peripheral is autmatically enabled and disabled as required to save power.
|
||||
//! Lowest power consumption can only be guaranteed if the send receive futures
|
||||
//! are dropped correctly (e.g. not using `mem::forget()`).
|
||||
|
||||
use bxcan;
|
||||
use bxcan::Interrupts;
|
||||
use core::future::Future;
|
||||
use embassy::interrupt::Interrupt;
|
||||
use embassy::util::InterruptFuture;
|
||||
use nb;
|
||||
use nb::block;
|
||||
|
||||
use crate::interrupt;
|
||||
|
||||
/// Interface to the Serial peripheral
|
||||
pub struct Can<T: Instance> {
|
||||
can: bxcan::Can<T>,
|
||||
tx_int: T::TInterrupt,
|
||||
rx_int: T::RInterrupt,
|
||||
}
|
||||
|
||||
impl<T: Instance> Can<T> {
|
||||
pub fn new(mut can: bxcan::Can<T>, tx_int: T::TInterrupt, rx_int: T::RInterrupt) -> Self {
|
||||
// Sync to the bus and start normal operation.
|
||||
can.enable_interrupts(
|
||||
Interrupts::TRANSMIT_MAILBOX_EMPTY | Interrupts::FIFO0_MESSAGE_PENDING,
|
||||
);
|
||||
block!(can.enable()).unwrap();
|
||||
|
||||
Can {
|
||||
can: can,
|
||||
tx_int: tx_int,
|
||||
rx_int: rx_int,
|
||||
}
|
||||
}
|
||||
|
||||
/// Sends can frame.
|
||||
///
|
||||
/// This method async-blocks until the frame is transmitted.
|
||||
pub fn transmit<'a>(&'a mut self, frame: &'a bxcan::Frame) -> impl Future<Output = ()> + 'a {
|
||||
async move {
|
||||
let fut = InterruptFuture::new(&mut self.tx_int);
|
||||
// Infallible
|
||||
self.can.transmit(frame).unwrap();
|
||||
|
||||
fut.await;
|
||||
}
|
||||
}
|
||||
|
||||
/// Receive can frame.
|
||||
///
|
||||
/// This method async-blocks until the frame is received.
|
||||
pub fn receive<'a>(&'a mut self) -> impl Future<Output = bxcan::Frame> + 'a {
|
||||
async move {
|
||||
let mut frame: Option<bxcan::Frame>;
|
||||
|
||||
loop {
|
||||
let fut = InterruptFuture::new(&mut self.rx_int);
|
||||
frame = match self.can.receive() {
|
||||
Ok(frame) => Some(frame),
|
||||
Err(nb::Error::WouldBlock) => None,
|
||||
Err(nb::Error::Other(_)) => None, // Ignore overrun errors.
|
||||
};
|
||||
if frame.is_some() {
|
||||
break;
|
||||
}
|
||||
fut.await;
|
||||
}
|
||||
|
||||
frame.unwrap()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mod private {
|
||||
pub trait Sealed {}
|
||||
}
|
||||
|
||||
pub trait Instance: bxcan::Instance + private::Sealed {
|
||||
type TInterrupt: Interrupt;
|
||||
type RInterrupt: Interrupt;
|
||||
}
|
||||
|
||||
macro_rules! can {
|
||||
($($can:ident => ($tint:ident, $rint:ident),)+) => {
|
||||
$(
|
||||
impl private::Sealed for crate::hal::can::Can<crate::pac::$can> {}
|
||||
impl Instance for crate::hal::can::Can<crate::pac::$can> {
|
||||
type TInterrupt = interrupt::$tint;
|
||||
type RInterrupt = interrupt::$rint;
|
||||
}
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
can! {
|
||||
CAN1 => (CAN1_TX, CAN1_RX0),
|
||||
CAN2 => (CAN2_TX, CAN2_RX0),
|
||||
}
|
||||
@ -1,790 +0,0 @@
|
||||
use core::future::Future;
|
||||
use core::mem;
|
||||
use cortex_m;
|
||||
|
||||
use crate::hal::gpio;
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
use crate::hal::syscfg::SysCfg;
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
use crate::hal::syscfg::SYSCFG as SysCfg;
|
||||
|
||||
use embassy::traits::gpio::{
|
||||
WaitForAnyEdge, WaitForFallingEdge, WaitForHigh, WaitForLow, WaitForRisingEdge,
|
||||
};
|
||||
use embassy::util::InterruptFuture;
|
||||
|
||||
use embedded_hal::digital::v2 as digital;
|
||||
|
||||
use crate::interrupt;
|
||||
|
||||
pub struct ExtiPin<T: Instance> {
|
||||
pin: T,
|
||||
interrupt: T::Interrupt,
|
||||
}
|
||||
|
||||
impl<T: Instance> ExtiPin<T> {
|
||||
pub fn new(mut pin: T, interrupt: T::Interrupt, syscfg: &mut SysCfg) -> Self {
|
||||
critical_section::with(|_| {
|
||||
pin.make_source(syscfg);
|
||||
});
|
||||
|
||||
Self { pin, interrupt }
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance + digital::OutputPin> digital::OutputPin for ExtiPin<T> {
|
||||
type Error = T::Error;
|
||||
|
||||
fn set_low(&mut self) -> Result<(), Self::Error> {
|
||||
self.pin.set_low()
|
||||
}
|
||||
|
||||
fn set_high(&mut self) -> Result<(), Self::Error> {
|
||||
self.pin.set_high()
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance + digital::StatefulOutputPin> digital::StatefulOutputPin for ExtiPin<T> {
|
||||
fn is_set_low(&self) -> Result<bool, Self::Error> {
|
||||
self.pin.is_set_low()
|
||||
}
|
||||
|
||||
fn is_set_high(&self) -> Result<bool, Self::Error> {
|
||||
self.pin.is_set_high()
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance + digital::ToggleableOutputPin> digital::ToggleableOutputPin for ExtiPin<T> {
|
||||
type Error = T::Error;
|
||||
|
||||
fn toggle(&mut self) -> Result<(), Self::Error> {
|
||||
self.pin.toggle()
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance + digital::InputPin> digital::InputPin for ExtiPin<T> {
|
||||
type Error = T::Error;
|
||||
|
||||
fn is_high(&self) -> Result<bool, Self::Error> {
|
||||
self.pin.is_high()
|
||||
}
|
||||
|
||||
fn is_low(&self) -> Result<bool, Self::Error> {
|
||||
self.pin.is_low()
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance + digital::InputPin + 'static> ExtiPin<T> {
|
||||
fn wait_for_state<'a>(&'a mut self, state: bool) -> impl Future<Output = ()> + 'a {
|
||||
async move {
|
||||
let fut = InterruptFuture::new(&mut self.interrupt);
|
||||
let pin = &mut self.pin;
|
||||
critical_section::with(|_| {
|
||||
pin.trigger_edge(if state {
|
||||
EdgeOption::Rising
|
||||
} else {
|
||||
EdgeOption::Falling
|
||||
});
|
||||
});
|
||||
|
||||
if (state && self.pin.is_high().unwrap_or(false))
|
||||
|| (!state && self.pin.is_low().unwrap_or(false))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
fut.await;
|
||||
|
||||
self.pin.clear_pending_bit();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance + 'static> ExtiPin<T> {
|
||||
fn wait_for_edge<'a>(&'a mut self, state: EdgeOption) -> impl Future<Output = ()> + 'a {
|
||||
self.pin.clear_pending_bit();
|
||||
async move {
|
||||
let fut = InterruptFuture::new(&mut self.interrupt);
|
||||
let pin = &mut self.pin;
|
||||
critical_section::with(|_| {
|
||||
pin.trigger_edge(state);
|
||||
});
|
||||
|
||||
fut.await;
|
||||
|
||||
self.pin.clear_pending_bit();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance + digital::InputPin + 'static> WaitForHigh for ExtiPin<T> {
|
||||
type Future<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn wait_for_high<'a>(&'a mut self) -> Self::Future<'a> {
|
||||
self.wait_for_state(true)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance + digital::InputPin + 'static> WaitForLow for ExtiPin<T> {
|
||||
type Future<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn wait_for_low<'a>(&'a mut self) -> Self::Future<'a> {
|
||||
self.wait_for_state(false)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
Irq Handler Description
|
||||
EXTI0_IRQn EXTI0_IRQHandler Handler for pins connected to line 0
|
||||
EXTI1_IRQn EXTI1_IRQHandler Handler for pins connected to line 1
|
||||
EXTI2_IRQn EXTI2_IRQHandler Handler for pins connected to line 2
|
||||
EXTI3_IRQn EXTI3_IRQHandler Handler for pins connected to line 3
|
||||
EXTI4_IRQn EXTI4_IRQHandler Handler for pins connected to line 4
|
||||
EXTI9_5_IRQn EXTI9_5_IRQHandler Handler for pins connected to line 5 to 9
|
||||
EXTI15_10_IRQn EXTI15_10_IRQHandler Handler for pins connected to line 10 to 15
|
||||
*/
|
||||
|
||||
impl<T: Instance + 'static> WaitForRisingEdge for ExtiPin<T> {
|
||||
type Future<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn wait_for_rising_edge<'a>(&'a mut self) -> Self::Future<'a> {
|
||||
self.wait_for_edge(EdgeOption::Rising)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance + 'static> WaitForFallingEdge for ExtiPin<T> {
|
||||
type Future<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn wait_for_falling_edge<'a>(&'a mut self) -> Self::Future<'a> {
|
||||
self.wait_for_edge(EdgeOption::Falling)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance + 'static> WaitForAnyEdge for ExtiPin<T> {
|
||||
type Future<'a> = impl Future<Output = ()> + 'a;
|
||||
|
||||
fn wait_for_any_edge<'a>(&'a mut self) -> Self::Future<'a> {
|
||||
self.wait_for_edge(EdgeOption::RisingFalling)
|
||||
}
|
||||
}
|
||||
|
||||
mod private {
|
||||
pub trait Sealed {}
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
pub enum EdgeOption {
|
||||
Rising,
|
||||
Falling,
|
||||
RisingFalling,
|
||||
}
|
||||
|
||||
pub trait WithInterrupt: private::Sealed {
|
||||
type Interrupt: interrupt::Interrupt;
|
||||
}
|
||||
|
||||
pub trait Instance: WithInterrupt {
|
||||
fn make_source(&mut self, syscfg: &mut SysCfg);
|
||||
fn clear_pending_bit(&mut self);
|
||||
fn trigger_edge(&mut self, edge: EdgeOption);
|
||||
}
|
||||
|
||||
macro_rules! exti {
|
||||
($set:ident, [
|
||||
$($INT:ident => $pin:ident,)+
|
||||
]) => {
|
||||
$(
|
||||
impl<T> private::Sealed for gpio::$set::$pin<T> {}
|
||||
impl<T> WithInterrupt for gpio::$set::$pin<T> {
|
||||
type Interrupt = interrupt::$INT;
|
||||
}
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
impl<T> Instance for gpio::$set::$pin<gpio::Input<T>> {
|
||||
fn make_source(&mut self, syscfg: &mut SysCfg) {
|
||||
use crate::hal::gpio::ExtiPin;
|
||||
self.make_interrupt_source(syscfg);
|
||||
}
|
||||
|
||||
fn clear_pending_bit(&mut self) {
|
||||
use crate::hal::{gpio::Edge, gpio::ExtiPin, syscfg::SysCfg};
|
||||
|
||||
self.clear_interrupt_pending_bit();
|
||||
}
|
||||
|
||||
fn trigger_edge(&mut self, edge: EdgeOption) {
|
||||
use crate::hal::{gpio::Edge, gpio::ExtiPin, syscfg::SysCfg};
|
||||
use crate::pac::EXTI;
|
||||
let mut exti: EXTI = unsafe { mem::transmute(()) };
|
||||
let edge = match edge {
|
||||
EdgeOption::Falling => Edge::FALLING,
|
||||
EdgeOption::Rising => Edge::RISING,
|
||||
EdgeOption::RisingFalling => Edge::RISING_FALLING,
|
||||
};
|
||||
self.trigger_on_edge(&mut exti, edge);
|
||||
self.enable_interrupt(&mut exti);
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
impl<T> Instance for gpio::$set::$pin<T> {
|
||||
fn make_source(&mut self, syscfg: &mut SysCfg) {}
|
||||
|
||||
fn clear_pending_bit(&mut self) {
|
||||
use crate::hal::{
|
||||
exti::{Exti, ExtiLine, GpioLine, TriggerEdge},
|
||||
syscfg::SYSCFG,
|
||||
};
|
||||
|
||||
Exti::unpend(GpioLine::from_raw_line(self.pin_number()).unwrap());
|
||||
}
|
||||
|
||||
fn trigger_edge(&mut self, edge: EdgeOption) {
|
||||
use crate::hal::{
|
||||
exti::{Exti, ExtiLine, GpioLine, TriggerEdge},
|
||||
syscfg::SYSCFG,
|
||||
};
|
||||
|
||||
use crate::pac::EXTI;
|
||||
|
||||
let edge = match edge {
|
||||
EdgeOption::Falling => TriggerEdge::Falling,
|
||||
EdgeOption::Rising => TriggerEdge::Rising,
|
||||
EdgeOption::RisingFalling => TriggerEdge::Both,
|
||||
};
|
||||
|
||||
let exti: EXTI = unsafe { mem::transmute(()) };
|
||||
let mut exti = Exti::new(exti);
|
||||
let port = self.port();
|
||||
let mut syscfg: SYSCFG = unsafe { mem::transmute(()) };
|
||||
let line = GpioLine::from_raw_line(self.pin_number()).unwrap();
|
||||
exti.listen_gpio(&mut syscfg, port, line, edge);
|
||||
}
|
||||
}
|
||||
)+
|
||||
};
|
||||
}
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpioa, [
|
||||
EXTI0 => PA0,
|
||||
EXTI1 => PA1,
|
||||
EXTI2 => PA2,
|
||||
EXTI3 => PA3,
|
||||
EXTI4 => PA4,
|
||||
EXTI9_5 => PA5,
|
||||
EXTI9_5 => PA6,
|
||||
EXTI9_5 => PA7,
|
||||
EXTI9_5 => PA8,
|
||||
EXTI9_5 => PA9,
|
||||
EXTI15_10 => PA10,
|
||||
EXTI15_10 => PA11,
|
||||
EXTI15_10 => PA12,
|
||||
EXTI15_10 => PA13,
|
||||
EXTI15_10 => PA14,
|
||||
EXTI15_10 => PA15,
|
||||
]);
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpiob, [
|
||||
EXTI0 => PB0,
|
||||
EXTI1 => PB1,
|
||||
EXTI2 => PB2,
|
||||
EXTI3 => PB3,
|
||||
EXTI4 => PB4,
|
||||
EXTI9_5 => PB5,
|
||||
EXTI9_5 => PB6,
|
||||
EXTI9_5 => PB7,
|
||||
EXTI9_5 => PB8,
|
||||
EXTI9_5 => PB9,
|
||||
EXTI15_10 => PB10,
|
||||
EXTI15_10 => PB11,
|
||||
EXTI15_10 => PB12,
|
||||
EXTI15_10 => PB13,
|
||||
EXTI15_10 => PB14,
|
||||
EXTI15_10 => PB15,
|
||||
]);
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpioc, [
|
||||
EXTI0 => PC0,
|
||||
EXTI1 => PC1,
|
||||
EXTI2 => PC2,
|
||||
EXTI3 => PC3,
|
||||
EXTI4 => PC4,
|
||||
EXTI9_5 => PC5,
|
||||
EXTI9_5 => PC6,
|
||||
EXTI9_5 => PC7,
|
||||
EXTI9_5 => PC8,
|
||||
EXTI9_5 => PC9,
|
||||
EXTI15_10 => PC10,
|
||||
EXTI15_10 => PC11,
|
||||
EXTI15_10 => PC12,
|
||||
EXTI15_10 => PC13,
|
||||
EXTI15_10 => PC14,
|
||||
EXTI15_10 => PC15,
|
||||
]);
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpiod, [
|
||||
EXTI0 => PD0,
|
||||
EXTI1 => PD1,
|
||||
EXTI2 => PD2,
|
||||
EXTI3 => PD3,
|
||||
EXTI4 => PD4,
|
||||
EXTI9_5 => PD5,
|
||||
EXTI9_5 => PD6,
|
||||
EXTI9_5 => PD7,
|
||||
EXTI9_5 => PD8,
|
||||
EXTI9_5 => PD9,
|
||||
EXTI15_10 => PD10,
|
||||
EXTI15_10 => PD11,
|
||||
EXTI15_10 => PD12,
|
||||
EXTI15_10 => PD13,
|
||||
EXTI15_10 => PD14,
|
||||
EXTI15_10 => PD15,
|
||||
]);
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpioe, [
|
||||
EXTI0 => PE0,
|
||||
EXTI1 => PE1,
|
||||
EXTI2 => PE2,
|
||||
EXTI3 => PE3,
|
||||
EXTI4 => PE4,
|
||||
EXTI9_5 => PE5,
|
||||
EXTI9_5 => PE6,
|
||||
EXTI9_5 => PE7,
|
||||
EXTI9_5 => PE8,
|
||||
EXTI9_5 => PE9,
|
||||
EXTI15_10 => PE10,
|
||||
EXTI15_10 => PE11,
|
||||
EXTI15_10 => PE12,
|
||||
EXTI15_10 => PE13,
|
||||
EXTI15_10 => PE14,
|
||||
EXTI15_10 => PE15,
|
||||
]);
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpiof, [
|
||||
EXTI0 => PF0,
|
||||
EXTI1 => PF1,
|
||||
EXTI2 => PF2,
|
||||
EXTI3 => PF3,
|
||||
EXTI4 => PF4,
|
||||
EXTI9_5 => PF5,
|
||||
EXTI9_5 => PF6,
|
||||
EXTI9_5 => PF7,
|
||||
EXTI9_5 => PF8,
|
||||
EXTI9_5 => PF9,
|
||||
EXTI15_10 => PF10,
|
||||
EXTI15_10 => PF11,
|
||||
EXTI15_10 => PF12,
|
||||
EXTI15_10 => PF13,
|
||||
EXTI15_10 => PF14,
|
||||
EXTI15_10 => PF15,
|
||||
]);
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpiog, [
|
||||
EXTI0 => PG0,
|
||||
EXTI1 => PG1,
|
||||
EXTI2 => PG2,
|
||||
EXTI3 => PG3,
|
||||
EXTI4 => PG4,
|
||||
EXTI9_5 => PG5,
|
||||
EXTI9_5 => PG6,
|
||||
EXTI9_5 => PG7,
|
||||
EXTI9_5 => PG8,
|
||||
EXTI9_5 => PG9,
|
||||
EXTI15_10 => PG10,
|
||||
EXTI15_10 => PG11,
|
||||
EXTI15_10 => PG12,
|
||||
EXTI15_10 => PG13,
|
||||
EXTI15_10 => PG14,
|
||||
EXTI15_10 => PG15,
|
||||
]);
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpioh, [
|
||||
EXTI0 => PH0,
|
||||
EXTI1 => PH1,
|
||||
EXTI2 => PH2,
|
||||
EXTI3 => PH3,
|
||||
EXTI4 => PH4,
|
||||
EXTI9_5 => PH5,
|
||||
EXTI9_5 => PH6,
|
||||
EXTI9_5 => PH7,
|
||||
EXTI9_5 => PH8,
|
||||
EXTI9_5 => PH9,
|
||||
EXTI15_10 => PH10,
|
||||
EXTI15_10 => PH11,
|
||||
EXTI15_10 => PH12,
|
||||
EXTI15_10 => PH13,
|
||||
EXTI15_10 => PH14,
|
||||
EXTI15_10 => PH15,
|
||||
]);
|
||||
|
||||
#[cfg(any(feature = "stm32f401"))]
|
||||
exti!(gpioh, [
|
||||
EXTI0 => PH0,
|
||||
EXTI1 => PH1,
|
||||
]);
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpioi, [
|
||||
EXTI0 => PI0,
|
||||
EXTI1 => PI1,
|
||||
EXTI2 => PI2,
|
||||
EXTI3 => PI3,
|
||||
EXTI4 => PI4,
|
||||
EXTI9_5 => PI5,
|
||||
EXTI9_5 => PI6,
|
||||
EXTI9_5 => PI7,
|
||||
EXTI9_5 => PI8,
|
||||
EXTI9_5 => PI9,
|
||||
EXTI15_10 => PI10,
|
||||
EXTI15_10 => PI11,
|
||||
EXTI15_10 => PI12,
|
||||
EXTI15_10 => PI13,
|
||||
EXTI15_10 => PI14,
|
||||
EXTI15_10 => PI15,
|
||||
]);
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpioj, [
|
||||
EXTI0 => PJ0,
|
||||
EXTI1 => PJ1,
|
||||
EXTI2 => PJ2,
|
||||
EXTI3 => PJ3,
|
||||
EXTI4 => PJ4,
|
||||
EXTI9_5 => PJ5,
|
||||
EXTI9_5 => PJ6,
|
||||
EXTI9_5 => PJ7,
|
||||
EXTI9_5 => PJ8,
|
||||
EXTI9_5 => PJ9,
|
||||
EXTI15_10 => PJ10,
|
||||
EXTI15_10 => PJ11,
|
||||
EXTI15_10 => PJ12,
|
||||
EXTI15_10 => PJ13,
|
||||
EXTI15_10 => PJ14,
|
||||
EXTI15_10 => PJ15,
|
||||
]);
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479"
|
||||
))]
|
||||
exti!(gpiok, [
|
||||
EXTI0 => PK0,
|
||||
EXTI1 => PK1,
|
||||
EXTI2 => PK2,
|
||||
EXTI3 => PK3,
|
||||
EXTI4 => PK4,
|
||||
EXTI9_5 => PK5,
|
||||
EXTI9_5 => PK6,
|
||||
EXTI9_5 => PK7,
|
||||
]);
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
exti!(gpioa, [
|
||||
EXTI0_1 => PA0,
|
||||
EXTI0_1 => PA1,
|
||||
EXTI2_3 => PA2,
|
||||
EXTI2_3 => PA3,
|
||||
EXTI4_15 => PA4,
|
||||
EXTI4_15 => PA5,
|
||||
EXTI4_15 => PA6,
|
||||
EXTI4_15 => PA7,
|
||||
EXTI4_15 => PA8,
|
||||
EXTI4_15 => PA9,
|
||||
EXTI4_15 => PA10,
|
||||
EXTI4_15 => PA11,
|
||||
EXTI4_15 => PA12,
|
||||
EXTI4_15 => PA13,
|
||||
EXTI4_15 => PA14,
|
||||
EXTI4_15 => PA15,
|
||||
]);
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
exti!(gpiob, [
|
||||
EXTI0_1 => PB0,
|
||||
EXTI0_1 => PB1,
|
||||
EXTI2_3 => PB2,
|
||||
EXTI2_3 => PB3,
|
||||
EXTI4_15 => PB4,
|
||||
EXTI4_15 => PB5,
|
||||
EXTI4_15 => PB6,
|
||||
EXTI4_15 => PB7,
|
||||
EXTI4_15 => PB8,
|
||||
EXTI4_15 => PB9,
|
||||
EXTI4_15 => PB10,
|
||||
EXTI4_15 => PB11,
|
||||
EXTI4_15 => PB12,
|
||||
EXTI4_15 => PB13,
|
||||
EXTI4_15 => PB14,
|
||||
EXTI4_15 => PB15,
|
||||
]);
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
exti!(gpioc, [
|
||||
EXTI0_1 => PC0,
|
||||
EXTI0_1 => PC1,
|
||||
EXTI2_3 => PC2,
|
||||
EXTI2_3 => PC3,
|
||||
EXTI4_15 => PC4,
|
||||
EXTI4_15 => PC5,
|
||||
EXTI4_15 => PC6,
|
||||
EXTI4_15 => PC7,
|
||||
EXTI4_15 => PC8,
|
||||
EXTI4_15 => PC9,
|
||||
EXTI4_15 => PC10,
|
||||
EXTI4_15 => PC11,
|
||||
EXTI4_15 => PC12,
|
||||
EXTI4_15 => PC13,
|
||||
EXTI4_15 => PC14,
|
||||
EXTI4_15 => PC15,
|
||||
]);
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
exti!(gpiod, [
|
||||
EXTI0_1 => PD0,
|
||||
EXTI0_1 => PD1,
|
||||
EXTI2_3 => PD2,
|
||||
EXTI2_3 => PD3,
|
||||
EXTI4_15 => PD4,
|
||||
EXTI4_15 => PD5,
|
||||
EXTI4_15 => PD6,
|
||||
EXTI4_15 => PD7,
|
||||
EXTI4_15 => PD8,
|
||||
EXTI4_15 => PD9,
|
||||
EXTI4_15 => PD10,
|
||||
EXTI4_15 => PD11,
|
||||
EXTI4_15 => PD12,
|
||||
EXTI4_15 => PD13,
|
||||
EXTI4_15 => PD14,
|
||||
EXTI4_15 => PD15,
|
||||
]);
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
exti!(gpioe, [
|
||||
EXTI0_1 => PE0,
|
||||
EXTI0_1 => PE1,
|
||||
EXTI2_3 => PE2,
|
||||
EXTI2_3 => PE3,
|
||||
EXTI4_15 => PE4,
|
||||
EXTI4_15 => PE5,
|
||||
EXTI4_15 => PE6,
|
||||
EXTI4_15 => PE7,
|
||||
EXTI4_15 => PE8,
|
||||
EXTI4_15 => PE9,
|
||||
EXTI4_15 => PE10,
|
||||
EXTI4_15 => PE11,
|
||||
EXTI4_15 => PE12,
|
||||
EXTI4_15 => PE13,
|
||||
EXTI4_15 => PE14,
|
||||
EXTI4_15 => PE15,
|
||||
]);
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
exti!(gpioh, [
|
||||
EXTI0_1 => PH0,
|
||||
EXTI0_1 => PH1,
|
||||
EXTI4_15 => PH9,
|
||||
EXTI4_15 => PH10,
|
||||
]);
|
||||
@ -1,4 +0,0 @@
|
||||
pub mod rtc;
|
||||
pub mod serial;
|
||||
pub mod spi;
|
||||
pub mod system;
|
||||
@ -1,505 +0,0 @@
|
||||
use crate::hal::bb;
|
||||
use crate::hal::rcc::Clocks;
|
||||
use core::cell::Cell;
|
||||
use core::convert::TryInto;
|
||||
use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
|
||||
use critical_section::CriticalSection;
|
||||
use embassy::interrupt::InterruptExt;
|
||||
use embassy::time::{Clock, TICKS_PER_SECOND};
|
||||
use embassy::util::CriticalSectionMutex as Mutex;
|
||||
|
||||
use crate::interrupt;
|
||||
use crate::interrupt::Interrupt;
|
||||
|
||||
// RTC timekeeping works with something we call "periods", which are time intervals
|
||||
// of 2^15 ticks. The RTC counter value is 16 bits, so one "overflow cycle" is 2 periods.
|
||||
//
|
||||
// A `period` count is maintained in parallel to the RTC hardware `counter`, like this:
|
||||
// - `period` and `counter` start at 0
|
||||
// - `period` is incremented on overflow (at counter value 0)
|
||||
// - `period` is incremented "midway" between overflows (at counter value 0x8000)
|
||||
//
|
||||
// Therefore, when `period` is even, counter is in 0..0x7FFF. When odd, counter is in 0x8000..0xFFFF
|
||||
// This allows for now() to return the correct value even if it races an overflow.
|
||||
//
|
||||
// To get `now()`, `period` is read first, then `counter` is read. If the counter value matches
|
||||
// the expected range for the `period` parity, we're done. If it doesn't, this means that
|
||||
// a new period start has raced us between reading `period` and `counter`, so we assume the `counter` value
|
||||
// corresponds to the next period.
|
||||
//
|
||||
// `period` is a 32bit integer, so It overflows on 2^32 * 2^15 / 32768 seconds of uptime, which is 136 years.
|
||||
fn calc_now(period: u32, counter: u16) -> u64 {
|
||||
((period as u64) << 15) + ((counter as u32 ^ ((period & 1) << 15)) as u64)
|
||||
}
|
||||
|
||||
struct AlarmState {
|
||||
timestamp: Cell<u64>,
|
||||
callback: Cell<Option<(fn(*mut ()), *mut ())>>,
|
||||
}
|
||||
|
||||
impl AlarmState {
|
||||
fn new() -> Self {
|
||||
Self {
|
||||
timestamp: Cell::new(u64::MAX),
|
||||
callback: Cell::new(None),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// TODO: This is sometimes wasteful, try to find a better way
|
||||
const ALARM_COUNT: usize = 3;
|
||||
|
||||
/// RTC timer that can be used by the executor and to set alarms.
|
||||
///
|
||||
/// It can work with Timers 2, 3, 4, 5, 9 and 12. Timers 9 and 12 only have one alarm available,
|
||||
/// while the others have three each.
|
||||
/// This timer works internally with a unit of 2^15 ticks, which means that if a call to
|
||||
/// [`embassy::time::Clock::now`] is blocked for that amount of ticks the returned value will be
|
||||
/// wrong (an old value). The current default tick rate is 32768 ticks per second.
|
||||
pub struct RTC<T: Instance> {
|
||||
rtc: T,
|
||||
irq: T::Interrupt,
|
||||
|
||||
/// Number of 2^23 periods elapsed since boot.
|
||||
period: AtomicU32,
|
||||
|
||||
/// Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled.
|
||||
alarms: Mutex<[AlarmState; ALARM_COUNT]>,
|
||||
|
||||
clocks: Clocks,
|
||||
}
|
||||
|
||||
impl<T: Instance> RTC<T> {
|
||||
pub fn new(rtc: T, irq: T::Interrupt, clocks: Clocks) -> Self {
|
||||
Self {
|
||||
rtc,
|
||||
irq,
|
||||
period: AtomicU32::new(0),
|
||||
alarms: Mutex::new([AlarmState::new(), AlarmState::new(), AlarmState::new()]),
|
||||
clocks,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn start(&'static self) {
|
||||
self.rtc.enable_clock();
|
||||
self.rtc.stop_and_reset();
|
||||
|
||||
let multiplier = if T::ppre(&self.clocks) == 1 { 1 } else { 2 };
|
||||
let freq = T::pclk(&self.clocks) * multiplier;
|
||||
let psc = freq / TICKS_PER_SECOND as u32 - 1;
|
||||
let psc: u16 = psc.try_into().unwrap();
|
||||
|
||||
self.rtc.set_psc_arr(psc, u16::MAX);
|
||||
// Mid-way point
|
||||
self.rtc.set_compare(0, 0x8000);
|
||||
self.rtc.set_compare_interrupt(0, true);
|
||||
|
||||
self.irq.set_handler(|ptr| unsafe {
|
||||
let this = &*(ptr as *const () as *const Self);
|
||||
this.on_interrupt();
|
||||
});
|
||||
self.irq.set_handler_context(self as *const _ as *mut _);
|
||||
self.irq.unpend();
|
||||
self.irq.enable();
|
||||
|
||||
self.rtc.start();
|
||||
}
|
||||
|
||||
fn on_interrupt(&self) {
|
||||
if self.rtc.overflow_interrupt_status() {
|
||||
self.rtc.overflow_clear_flag();
|
||||
self.next_period();
|
||||
}
|
||||
|
||||
// Half overflow
|
||||
if self.rtc.compare_interrupt_status(0) {
|
||||
self.rtc.compare_clear_flag(0);
|
||||
self.next_period();
|
||||
}
|
||||
|
||||
for n in 1..=ALARM_COUNT {
|
||||
if self.rtc.compare_interrupt_status(n) {
|
||||
self.rtc.compare_clear_flag(n);
|
||||
critical_section::with(|cs| self.trigger_alarm(n, cs));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn next_period(&self) {
|
||||
critical_section::with(|cs| {
|
||||
let period = self.period.fetch_add(1, Ordering::Relaxed) + 1;
|
||||
let t = (period as u64) << 15;
|
||||
|
||||
for n in 1..=ALARM_COUNT {
|
||||
let alarm = &self.alarms.borrow(cs)[n - 1];
|
||||
let at = alarm.timestamp.get();
|
||||
|
||||
let diff = at - t;
|
||||
if diff < 0xc000 {
|
||||
self.rtc.set_compare(n, at as u16);
|
||||
self.rtc.set_compare_interrupt(n, true);
|
||||
}
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
fn trigger_alarm(&self, n: usize, cs: CriticalSection) {
|
||||
self.rtc.set_compare_interrupt(n, false);
|
||||
|
||||
let alarm = &self.alarms.borrow(cs)[n - 1];
|
||||
alarm.timestamp.set(u64::MAX);
|
||||
|
||||
// Call after clearing alarm, so the callback can set another alarm.
|
||||
if let Some((f, ctx)) = alarm.callback.get() {
|
||||
f(ctx);
|
||||
}
|
||||
}
|
||||
|
||||
fn set_alarm_callback(&self, n: usize, callback: fn(*mut ()), ctx: *mut ()) {
|
||||
critical_section::with(|cs| {
|
||||
let alarm = &self.alarms.borrow(cs)[n - 1];
|
||||
alarm.callback.set(Some((callback, ctx)));
|
||||
})
|
||||
}
|
||||
|
||||
fn set_alarm(&self, n: usize, timestamp: u64) {
|
||||
critical_section::with(|cs| {
|
||||
let alarm = &self.alarms.borrow(cs)[n - 1];
|
||||
alarm.timestamp.set(timestamp);
|
||||
|
||||
let t = self.now();
|
||||
if timestamp <= t {
|
||||
self.trigger_alarm(n, cs);
|
||||
return;
|
||||
}
|
||||
|
||||
let diff = timestamp - t;
|
||||
if diff < 0xc000 {
|
||||
let safe_timestamp = timestamp.max(t + 3);
|
||||
self.rtc.set_compare(n, safe_timestamp as u16);
|
||||
self.rtc.set_compare_interrupt(n, true);
|
||||
} else {
|
||||
self.rtc.set_compare_interrupt(n, false);
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
pub fn alarm1(&'static self) -> Alarm<T> {
|
||||
Alarm { n: 1, rtc: self }
|
||||
}
|
||||
pub fn alarm2(&'static self) -> Option<Alarm<T>> {
|
||||
if T::REAL_ALARM_COUNT >= 2 {
|
||||
Some(Alarm { n: 2, rtc: self })
|
||||
} else {
|
||||
None
|
||||
}
|
||||
}
|
||||
pub fn alarm3(&'static self) -> Option<Alarm<T>> {
|
||||
if T::REAL_ALARM_COUNT >= 3 {
|
||||
Some(Alarm { n: 3, rtc: self })
|
||||
} else {
|
||||
None
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance> embassy::time::Clock for RTC<T> {
|
||||
fn now(&self) -> u64 {
|
||||
let period = self.period.load(Ordering::Relaxed);
|
||||
compiler_fence(Ordering::Acquire);
|
||||
let counter = self.rtc.counter();
|
||||
calc_now(period, counter)
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Alarm<T: Instance> {
|
||||
n: usize,
|
||||
rtc: &'static RTC<T>,
|
||||
}
|
||||
|
||||
impl<T: Instance> embassy::time::Alarm for Alarm<T> {
|
||||
fn set_callback(&self, callback: fn(*mut ()), ctx: *mut ()) {
|
||||
self.rtc.set_alarm_callback(self.n, callback, ctx);
|
||||
}
|
||||
|
||||
fn set(&self, timestamp: u64) {
|
||||
self.rtc.set_alarm(self.n, timestamp);
|
||||
}
|
||||
|
||||
fn clear(&self) {
|
||||
self.rtc.set_alarm(self.n, u64::MAX);
|
||||
}
|
||||
}
|
||||
|
||||
mod sealed {
|
||||
pub trait Sealed {}
|
||||
}
|
||||
|
||||
pub trait Instance: sealed::Sealed + Sized + 'static {
|
||||
type Interrupt: Interrupt;
|
||||
const REAL_ALARM_COUNT: usize;
|
||||
|
||||
fn enable_clock(&self);
|
||||
fn set_compare(&self, n: usize, value: u16);
|
||||
fn set_compare_interrupt(&self, n: usize, enable: bool);
|
||||
fn compare_interrupt_status(&self, n: usize) -> bool;
|
||||
fn compare_clear_flag(&self, n: usize);
|
||||
fn overflow_interrupt_status(&self) -> bool;
|
||||
fn overflow_clear_flag(&self);
|
||||
// This method should ensure that the values are really updated before returning
|
||||
fn set_psc_arr(&self, psc: u16, arr: u16);
|
||||
fn stop_and_reset(&self);
|
||||
fn start(&self);
|
||||
fn counter(&self) -> u16;
|
||||
fn ppre(clocks: &Clocks) -> u8;
|
||||
fn pclk(clocks: &Clocks) -> u32;
|
||||
}
|
||||
|
||||
#[allow(unused_macros)]
|
||||
macro_rules! impl_timer {
|
||||
($module:ident: ($TYPE:ident, $INT:ident, $apbenr:ident, $enrbit:expr, $apbrstr:ident, $rstrbit:expr, $ppre:ident, $pclk: ident), 3) => {
|
||||
mod $module {
|
||||
use super::*;
|
||||
use crate::hal::pac::{$TYPE, RCC};
|
||||
|
||||
impl sealed::Sealed for $TYPE {}
|
||||
|
||||
impl Instance for $TYPE {
|
||||
type Interrupt = interrupt::$INT;
|
||||
const REAL_ALARM_COUNT: usize = 3;
|
||||
|
||||
fn enable_clock(&self) {
|
||||
// NOTE(unsafe) It will only be used for atomic operations
|
||||
unsafe {
|
||||
let rcc = &*RCC::ptr();
|
||||
|
||||
bb::set(&rcc.$apbenr, $enrbit);
|
||||
bb::set(&rcc.$apbrstr, $rstrbit);
|
||||
bb::clear(&rcc.$apbrstr, $rstrbit);
|
||||
}
|
||||
}
|
||||
|
||||
fn set_compare(&self, n: usize, value: u16) {
|
||||
// NOTE(unsafe) these registers accept all the range of u16 values
|
||||
match n {
|
||||
0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
|
||||
1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
|
||||
2 => self.ccr3.write(|w| unsafe { w.bits(value.into()) }),
|
||||
3 => self.ccr4.write(|w| unsafe { w.bits(value.into()) }),
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
|
||||
fn set_compare_interrupt(&self, n: usize, enable: bool) {
|
||||
if n > 3 {
|
||||
return;
|
||||
}
|
||||
let bit = n as u8 + 1;
|
||||
unsafe {
|
||||
if enable {
|
||||
bb::set(&self.dier, bit);
|
||||
} else {
|
||||
bb::clear(&self.dier, bit);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn compare_interrupt_status(&self, n: usize) -> bool {
|
||||
let status = self.sr.read();
|
||||
match n {
|
||||
0 => status.cc1if().bit_is_set(),
|
||||
1 => status.cc2if().bit_is_set(),
|
||||
2 => status.cc3if().bit_is_set(),
|
||||
3 => status.cc4if().bit_is_set(),
|
||||
_ => false,
|
||||
}
|
||||
}
|
||||
|
||||
fn compare_clear_flag(&self, n: usize) {
|
||||
if n > 3 {
|
||||
return;
|
||||
}
|
||||
let bit = n as u8 + 1;
|
||||
unsafe {
|
||||
bb::clear(&self.sr, bit);
|
||||
}
|
||||
}
|
||||
|
||||
fn overflow_interrupt_status(&self) -> bool {
|
||||
self.sr.read().uif().bit_is_set()
|
||||
}
|
||||
|
||||
fn overflow_clear_flag(&self) {
|
||||
unsafe {
|
||||
bb::clear(&self.sr, 0);
|
||||
}
|
||||
}
|
||||
|
||||
fn set_psc_arr(&self, psc: u16, arr: u16) {
|
||||
// NOTE(unsafe) All u16 values are valid
|
||||
self.psc.write(|w| unsafe { w.bits(psc.into()) });
|
||||
self.arr.write(|w| unsafe { w.bits(arr.into()) });
|
||||
|
||||
unsafe {
|
||||
// Set URS, generate update, clear URS
|
||||
bb::set(&self.cr1, 2);
|
||||
self.egr.write(|w| w.ug().set_bit());
|
||||
bb::clear(&self.cr1, 2);
|
||||
}
|
||||
}
|
||||
|
||||
fn stop_and_reset(&self) {
|
||||
unsafe {
|
||||
bb::clear(&self.cr1, 0);
|
||||
}
|
||||
self.cnt.reset();
|
||||
}
|
||||
|
||||
fn start(&self) {
|
||||
unsafe { bb::set(&self.cr1, 0) }
|
||||
}
|
||||
|
||||
fn counter(&self) -> u16 {
|
||||
self.cnt.read().bits() as u16
|
||||
}
|
||||
|
||||
fn ppre(clocks: &Clocks) -> u8 {
|
||||
clocks.$ppre()
|
||||
}
|
||||
|
||||
fn pclk(clocks: &Clocks) -> u32 {
|
||||
clocks.$pclk().0
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
($module:ident: ($TYPE:ident, $INT:ident, $apbenr:ident, $enrbit:expr, $apbrstr:ident, $rstrbit:expr, $ppre:ident, $pclk: ident), 1) => {
|
||||
mod $module {
|
||||
use super::*;
|
||||
use crate::hal::pac::{$TYPE, RCC};
|
||||
|
||||
impl sealed::Sealed for $TYPE {}
|
||||
|
||||
impl Instance for $TYPE {
|
||||
type Interrupt = interrupt::$INT;
|
||||
const REAL_ALARM_COUNT: usize = 1;
|
||||
|
||||
fn enable_clock(&self) {
|
||||
// NOTE(unsafe) It will only be used for atomic operations
|
||||
unsafe {
|
||||
let rcc = &*RCC::ptr();
|
||||
|
||||
bb::set(&rcc.$apbenr, $enrbit);
|
||||
bb::set(&rcc.$apbrstr, $rstrbit);
|
||||
bb::clear(&rcc.$apbrstr, $rstrbit);
|
||||
}
|
||||
}
|
||||
|
||||
fn set_compare(&self, n: usize, value: u16) {
|
||||
// NOTE(unsafe) these registers accept all the range of u16 values
|
||||
match n {
|
||||
0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
|
||||
1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
|
||||
fn set_compare_interrupt(&self, n: usize, enable: bool) {
|
||||
if n > 1 {
|
||||
return;
|
||||
}
|
||||
let bit = n as u8 + 1;
|
||||
unsafe {
|
||||
if enable {
|
||||
bb::set(&self.dier, bit);
|
||||
} else {
|
||||
bb::clear(&self.dier, bit);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn compare_interrupt_status(&self, n: usize) -> bool {
|
||||
let status = self.sr.read();
|
||||
match n {
|
||||
0 => status.cc1if().bit_is_set(),
|
||||
1 => status.cc2if().bit_is_set(),
|
||||
_ => false,
|
||||
}
|
||||
}
|
||||
|
||||
fn compare_clear_flag(&self, n: usize) {
|
||||
if n > 1 {
|
||||
return;
|
||||
}
|
||||
let bit = n as u8 + 1;
|
||||
unsafe {
|
||||
bb::clear(&self.sr, bit);
|
||||
}
|
||||
}
|
||||
|
||||
fn overflow_interrupt_status(&self) -> bool {
|
||||
self.sr.read().uif().bit_is_set()
|
||||
}
|
||||
|
||||
fn overflow_clear_flag(&self) {
|
||||
unsafe {
|
||||
bb::clear(&self.sr, 0);
|
||||
}
|
||||
}
|
||||
|
||||
fn set_psc_arr(&self, psc: u16, arr: u16) {
|
||||
// NOTE(unsafe) All u16 values are valid
|
||||
self.psc.write(|w| unsafe { w.bits(psc.into()) });
|
||||
self.arr.write(|w| unsafe { w.bits(arr.into()) });
|
||||
|
||||
unsafe {
|
||||
// Set URS, generate update, clear URS
|
||||
bb::set(&self.cr1, 2);
|
||||
self.egr.write(|w| w.ug().set_bit());
|
||||
bb::clear(&self.cr1, 2);
|
||||
}
|
||||
}
|
||||
|
||||
fn stop_and_reset(&self) {
|
||||
unsafe {
|
||||
bb::clear(&self.cr1, 0);
|
||||
}
|
||||
self.cnt.reset();
|
||||
}
|
||||
|
||||
fn start(&self) {
|
||||
unsafe { bb::set(&self.cr1, 0) }
|
||||
}
|
||||
|
||||
fn counter(&self) -> u16 {
|
||||
self.cnt.read().bits() as u16
|
||||
}
|
||||
|
||||
fn ppre(clocks: &Clocks) -> u8 {
|
||||
clocks.$ppre()
|
||||
}
|
||||
|
||||
fn pclk(clocks: &Clocks) -> u32 {
|
||||
clocks.$pclk().0
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "stm32f410"))]
|
||||
impl_timer!(tim2: (TIM2, TIM2, apb1enr, 0, apb1rstr, 0, ppre1, pclk1), 3);
|
||||
|
||||
#[cfg(not(feature = "stm32f410"))]
|
||||
impl_timer!(tim3: (TIM3, TIM3, apb1enr, 1, apb1rstr, 1, ppre1, pclk1), 3);
|
||||
|
||||
#[cfg(not(feature = "stm32f410"))]
|
||||
impl_timer!(tim4: (TIM4, TIM4, apb1enr, 2, apb1rstr, 2, ppre1, pclk1), 3);
|
||||
|
||||
impl_timer!(tim5: (TIM5, TIM5, apb1enr, 3, apb1rstr, 3, ppre1, pclk1), 3);
|
||||
|
||||
impl_timer!(tim9: (TIM9, TIM1_BRK_TIM9, apb2enr, 16, apb2rstr, 16, ppre2, pclk2), 1);
|
||||
|
||||
#[cfg(not(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411")))]
|
||||
impl_timer!(tim12: (TIM12, TIM8_BRK_TIM12, apb1enr, 6, apb1rstr, 6, ppre1, pclk1), 1);
|
||||
@ -1,357 +0,0 @@
|
||||
//! Async Serial.
|
||||
|
||||
use core::future::Future;
|
||||
use core::marker::PhantomData;
|
||||
use embassy::interrupt::Interrupt;
|
||||
use embassy::traits::uart::{Error, Read, ReadUntilIdle, Write};
|
||||
use embassy::util::InterruptFuture;
|
||||
use futures::{select_biased, FutureExt};
|
||||
|
||||
use crate::hal::{
|
||||
dma,
|
||||
dma::config::DmaConfig,
|
||||
dma::traits::{Channel, DMASet, PeriAddress, Stream},
|
||||
dma::{MemoryToPeripheral, PeripheralToMemory, Transfer},
|
||||
rcc::Clocks,
|
||||
serial,
|
||||
serial::config::{Config as SerialConfig, DmaConfig as SerialDmaConfig},
|
||||
serial::{Event as SerialEvent, Pins},
|
||||
};
|
||||
use crate::interrupt;
|
||||
use crate::pac;
|
||||
|
||||
/// Interface to the Serial peripheral
|
||||
pub struct Serial<
|
||||
USART: PeriAddress<MemSize = u8> + WithInterrupt,
|
||||
TSTREAM: Stream + WithInterrupt,
|
||||
RSTREAM: Stream + WithInterrupt,
|
||||
CHANNEL: Channel,
|
||||
> {
|
||||
tx_stream: Option<TSTREAM>,
|
||||
rx_stream: Option<RSTREAM>,
|
||||
usart: Option<USART>,
|
||||
tx_int: TSTREAM::Interrupt,
|
||||
rx_int: RSTREAM::Interrupt,
|
||||
usart_int: USART::Interrupt,
|
||||
channel: PhantomData<CHANNEL>,
|
||||
}
|
||||
|
||||
// static mut INSTANCE: *const Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> = ptr::null_mut();
|
||||
|
||||
impl<USART, TSTREAM, RSTREAM, CHANNEL> Serial<USART, TSTREAM, RSTREAM, CHANNEL>
|
||||
where
|
||||
USART: serial::Instance
|
||||
+ PeriAddress<MemSize = u8>
|
||||
+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
|
||||
+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
|
||||
+ WithInterrupt,
|
||||
TSTREAM: Stream + WithInterrupt,
|
||||
RSTREAM: Stream + WithInterrupt,
|
||||
CHANNEL: Channel,
|
||||
{
|
||||
// Leaking futures is forbidden!
|
||||
pub unsafe fn new<PINS>(
|
||||
usart: USART,
|
||||
streams: (TSTREAM, RSTREAM),
|
||||
pins: PINS,
|
||||
tx_int: TSTREAM::Interrupt,
|
||||
rx_int: RSTREAM::Interrupt,
|
||||
usart_int: USART::Interrupt,
|
||||
mut config: SerialConfig,
|
||||
clocks: Clocks,
|
||||
) -> Self
|
||||
where
|
||||
PINS: Pins<USART>,
|
||||
{
|
||||
config.dma = SerialDmaConfig::TxRx;
|
||||
|
||||
let (usart, _) = serial::Serial::new(usart, pins, config, clocks)
|
||||
.unwrap()
|
||||
.release();
|
||||
|
||||
let (tx_stream, rx_stream) = streams;
|
||||
|
||||
Serial {
|
||||
tx_stream: Some(tx_stream),
|
||||
rx_stream: Some(rx_stream),
|
||||
usart: Some(usart),
|
||||
tx_int: tx_int,
|
||||
rx_int: rx_int,
|
||||
usart_int: usart_int,
|
||||
channel: PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<USART, TSTREAM, RSTREAM, CHANNEL> Read for Serial<USART, TSTREAM, RSTREAM, CHANNEL>
|
||||
where
|
||||
USART: serial::Instance
|
||||
+ PeriAddress<MemSize = u8>
|
||||
+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
|
||||
+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
|
||||
+ WithInterrupt
|
||||
+ 'static,
|
||||
TSTREAM: Stream + WithInterrupt + 'static,
|
||||
RSTREAM: Stream + WithInterrupt + 'static,
|
||||
CHANNEL: Channel + 'static,
|
||||
{
|
||||
type ReadFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
|
||||
|
||||
/// Receives serial data.
|
||||
///
|
||||
/// The future is pending until the buffer is completely filled.
|
||||
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
||||
let static_buf = unsafe { core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf) };
|
||||
|
||||
async move {
|
||||
let rx_stream = self.rx_stream.take().unwrap();
|
||||
let usart = self.usart.take().unwrap();
|
||||
|
||||
let mut rx_transfer = Transfer::init(
|
||||
rx_stream,
|
||||
usart,
|
||||
static_buf,
|
||||
None,
|
||||
DmaConfig::default()
|
||||
.transfer_complete_interrupt(true)
|
||||
.memory_increment(true)
|
||||
.double_buffer(false),
|
||||
);
|
||||
|
||||
let fut = InterruptFuture::new(&mut self.rx_int);
|
||||
rx_transfer.start(|_usart| {});
|
||||
fut.await;
|
||||
|
||||
let (rx_stream, usart, _, _) = rx_transfer.free();
|
||||
self.rx_stream.replace(rx_stream);
|
||||
self.usart.replace(usart);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<USART, TSTREAM, RSTREAM, CHANNEL> Write for Serial<USART, TSTREAM, RSTREAM, CHANNEL>
|
||||
where
|
||||
USART: serial::Instance
|
||||
+ PeriAddress<MemSize = u8>
|
||||
+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
|
||||
+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
|
||||
+ WithInterrupt
|
||||
+ 'static,
|
||||
TSTREAM: Stream + WithInterrupt + 'static,
|
||||
RSTREAM: Stream + WithInterrupt + 'static,
|
||||
CHANNEL: Channel + 'static,
|
||||
{
|
||||
type WriteFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
|
||||
|
||||
/// Sends serial data.
|
||||
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
||||
#[allow(mutable_transmutes)]
|
||||
let static_buf = unsafe { core::mem::transmute::<&'a [u8], &'static mut [u8]>(buf) };
|
||||
|
||||
async move {
|
||||
let tx_stream = self.tx_stream.take().unwrap();
|
||||
let usart = self.usart.take().unwrap();
|
||||
|
||||
let mut tx_transfer = Transfer::init(
|
||||
tx_stream,
|
||||
usart,
|
||||
static_buf,
|
||||
None,
|
||||
DmaConfig::default()
|
||||
.transfer_complete_interrupt(true)
|
||||
.memory_increment(true)
|
||||
.double_buffer(false),
|
||||
);
|
||||
|
||||
let fut = InterruptFuture::new(&mut self.tx_int);
|
||||
|
||||
tx_transfer.start(|_usart| {});
|
||||
fut.await;
|
||||
|
||||
let (tx_stream, usart, _buf, _) = tx_transfer.free();
|
||||
|
||||
self.tx_stream.replace(tx_stream);
|
||||
self.usart.replace(usart);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<USART, TSTREAM, RSTREAM, CHANNEL> ReadUntilIdle for Serial<USART, TSTREAM, RSTREAM, CHANNEL>
|
||||
where
|
||||
USART: serial::Instance
|
||||
+ PeriAddress<MemSize = u8>
|
||||
+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
|
||||
+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
|
||||
+ WithInterrupt
|
||||
+ 'static,
|
||||
TSTREAM: Stream + WithInterrupt + 'static,
|
||||
RSTREAM: Stream + WithInterrupt + 'static,
|
||||
CHANNEL: Channel + 'static,
|
||||
{
|
||||
type ReadUntilIdleFuture<'a> = impl Future<Output = Result<usize, Error>> + 'a;
|
||||
|
||||
/// Receives serial data.
|
||||
///
|
||||
/// The future is pending until either the buffer is completely full, or the RX line falls idle after receiving some data.
|
||||
///
|
||||
/// Returns the number of bytes read.
|
||||
fn read_until_idle<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadUntilIdleFuture<'a> {
|
||||
let static_buf = unsafe { core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf) };
|
||||
|
||||
async move {
|
||||
let rx_stream = self.rx_stream.take().unwrap();
|
||||
let usart = self.usart.take().unwrap();
|
||||
|
||||
unsafe {
|
||||
/* __HAL_UART_ENABLE_IT(&uart->UartHandle, UART_IT_IDLE); */
|
||||
(*USART::ptr()).cr1.modify(|_, w| w.idleie().set_bit());
|
||||
|
||||
/* __HAL_UART_CLEAR_IDLEFLAG(&uart->UartHandle); */
|
||||
(*USART::ptr()).sr.read();
|
||||
(*USART::ptr()).dr.read();
|
||||
};
|
||||
|
||||
let mut rx_transfer = Transfer::init(
|
||||
rx_stream,
|
||||
usart,
|
||||
static_buf,
|
||||
None,
|
||||
DmaConfig::default()
|
||||
.transfer_complete_interrupt(true)
|
||||
.memory_increment(true)
|
||||
.double_buffer(false),
|
||||
);
|
||||
|
||||
let total_bytes = RSTREAM::get_number_of_transfers() as usize;
|
||||
|
||||
let fut = InterruptFuture::new(&mut self.rx_int);
|
||||
let fut_idle = InterruptFuture::new(&mut self.usart_int);
|
||||
|
||||
rx_transfer.start(|_usart| {});
|
||||
|
||||
futures::future::select(fut, fut_idle).await;
|
||||
|
||||
let (rx_stream, usart, _, _) = rx_transfer.free();
|
||||
|
||||
let remaining_bytes = RSTREAM::get_number_of_transfers() as usize;
|
||||
|
||||
unsafe {
|
||||
(*USART::ptr()).cr1.modify(|_, w| w.idleie().clear_bit());
|
||||
}
|
||||
self.rx_stream.replace(rx_stream);
|
||||
self.usart.replace(usart);
|
||||
|
||||
Ok(total_bytes - remaining_bytes)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mod private {
|
||||
pub trait Sealed {}
|
||||
}
|
||||
|
||||
pub trait WithInterrupt: private::Sealed {
|
||||
type Interrupt: Interrupt;
|
||||
}
|
||||
|
||||
macro_rules! dma {
|
||||
($($PER:ident => ($dma:ident, $stream:ident),)+) => {
|
||||
$(
|
||||
impl private::Sealed for dma::$stream<pac::$dma> {}
|
||||
impl WithInterrupt for dma::$stream<pac::$dma> {
|
||||
type Interrupt = interrupt::$PER;
|
||||
}
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! usart {
|
||||
($($PER:ident => ($usart:ident),)+) => {
|
||||
$(
|
||||
impl private::Sealed for pac::$usart {}
|
||||
impl WithInterrupt for pac::$usart {
|
||||
type Interrupt = interrupt::$PER;
|
||||
}
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
||||
dma! {
|
||||
DMA2_STREAM0 => (DMA2, Stream0),
|
||||
DMA2_STREAM1 => (DMA2, Stream1),
|
||||
DMA2_STREAM2 => (DMA2, Stream2),
|
||||
DMA2_STREAM3 => (DMA2, Stream3),
|
||||
DMA2_STREAM4 => (DMA2, Stream4),
|
||||
DMA2_STREAM5 => (DMA2, Stream5),
|
||||
DMA2_STREAM6 => (DMA2, Stream6),
|
||||
DMA2_STREAM7 => (DMA2, Stream7),
|
||||
DMA1_STREAM0 => (DMA1, Stream0),
|
||||
DMA1_STREAM1 => (DMA1, Stream1),
|
||||
DMA1_STREAM2 => (DMA1, Stream2),
|
||||
DMA1_STREAM3 => (DMA1, Stream3),
|
||||
DMA1_STREAM4 => (DMA1, Stream4),
|
||||
DMA1_STREAM5 => (DMA1, Stream5),
|
||||
DMA1_STREAM6 => (DMA1, Stream6),
|
||||
}
|
||||
|
||||
#[cfg(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411",))]
|
||||
usart! {
|
||||
USART1 => (USART1),
|
||||
USART2 => (USART2),
|
||||
USART6 => (USART6),
|
||||
}
|
||||
|
||||
#[cfg(any(feature = "stm32f405", feature = "stm32f407"))]
|
||||
usart! {
|
||||
USART1 => (USART1),
|
||||
USART2 => (USART2),
|
||||
USART3 => (USART3),
|
||||
USART6 => (USART6),
|
||||
|
||||
UART4 => (UART4),
|
||||
UART5 => (UART5),
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32f412")]
|
||||
usart! {
|
||||
USART1 => (USART1),
|
||||
USART2 => (USART2),
|
||||
USART3 => (USART3),
|
||||
USART6 => (USART6),
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32f413")]
|
||||
usart! {
|
||||
USART1 => (USART1),
|
||||
USART2 => (USART2),
|
||||
USART3 => (USART3),
|
||||
USART6 => (USART6),
|
||||
USART7 => (USART7),
|
||||
USART8 => (USART8),
|
||||
|
||||
UART5 => (UART5),
|
||||
UART9 => (UART9),
|
||||
UART10 => (UART10),
|
||||
}
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469"
|
||||
))]
|
||||
usart! {
|
||||
USART1 => (USART1),
|
||||
USART2 => (USART2),
|
||||
USART3 => (USART3),
|
||||
USART6 => (USART6),
|
||||
|
||||
UART4 => (UART4),
|
||||
UART5 => (UART5),
|
||||
// UART7 => (UART7),
|
||||
// UART8 => (UART8),
|
||||
}
|
||||
@ -1,492 +0,0 @@
|
||||
//! Async SPI
|
||||
|
||||
use embassy::time;
|
||||
|
||||
use core::{future::Future, marker::PhantomData, mem, ops::Deref, pin::Pin, ptr};
|
||||
use embassy::{interrupt::Interrupt, traits::spi::FullDuplex, util::InterruptFuture};
|
||||
use nb;
|
||||
|
||||
pub use crate::hal::spi::{Mode, Phase, Polarity};
|
||||
use crate::hal::{
|
||||
bb, dma,
|
||||
dma::config::DmaConfig,
|
||||
dma::traits::{Channel, DMASet, PeriAddress, Stream},
|
||||
dma::{MemoryToPeripheral, PeripheralToMemory, Transfer},
|
||||
rcc::Clocks,
|
||||
spi::Pins,
|
||||
time::Hertz,
|
||||
};
|
||||
use crate::interrupt;
|
||||
use crate::pac;
|
||||
use futures::future;
|
||||
|
||||
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[non_exhaustive]
|
||||
pub enum Error {
|
||||
TxBufferTooLong,
|
||||
RxBufferTooLong,
|
||||
Overrun,
|
||||
ModeFault,
|
||||
Crc,
|
||||
}
|
||||
|
||||
fn read_sr<T: Instance>(spi: &T) -> nb::Result<u8, Error> {
|
||||
let sr = spi.sr.read();
|
||||
Err(if sr.ovr().bit_is_set() {
|
||||
nb::Error::Other(Error::Overrun)
|
||||
} else if sr.modf().bit_is_set() {
|
||||
nb::Error::Other(Error::ModeFault)
|
||||
} else if sr.crcerr().bit_is_set() {
|
||||
nb::Error::Other(Error::Crc)
|
||||
} else if sr.rxne().bit_is_set() {
|
||||
// NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
|
||||
// reading a half-word)
|
||||
return Ok(unsafe { ptr::read_volatile(&spi.dr as *const _ as *const u8) });
|
||||
} else {
|
||||
nb::Error::WouldBlock
|
||||
})
|
||||
}
|
||||
|
||||
fn write_sr<T: Instance>(spi: &T, byte: u8) -> nb::Result<(), Error> {
|
||||
let sr = spi.sr.read();
|
||||
Err(if sr.ovr().bit_is_set() {
|
||||
// Read from the DR to clear the OVR bit
|
||||
let _ = spi.dr.read();
|
||||
nb::Error::Other(Error::Overrun)
|
||||
} else if sr.modf().bit_is_set() {
|
||||
// Write to CR1 to clear MODF
|
||||
spi.cr1.modify(|_r, w| w);
|
||||
nb::Error::Other(Error::ModeFault)
|
||||
} else if sr.crcerr().bit_is_set() {
|
||||
// Clear the CRCERR bit
|
||||
spi.sr.modify(|_r, w| {
|
||||
w.crcerr().clear_bit();
|
||||
w
|
||||
});
|
||||
nb::Error::Other(Error::Crc)
|
||||
} else if sr.txe().bit_is_set() {
|
||||
// NOTE(write_volatile) see note above
|
||||
unsafe { ptr::write_volatile(&spi.dr as *const _ as *mut u8, byte) }
|
||||
return Ok(());
|
||||
} else {
|
||||
nb::Error::WouldBlock
|
||||
})
|
||||
}
|
||||
|
||||
/// Interface to the Serial peripheral
|
||||
pub struct Spi<
|
||||
SPI: PeriAddress<MemSize = u8> + WithInterrupt,
|
||||
TSTREAM: Stream + WithInterrupt,
|
||||
RSTREAM: Stream + WithInterrupt,
|
||||
CHANNEL: Channel,
|
||||
> {
|
||||
tx_stream: Option<TSTREAM>,
|
||||
rx_stream: Option<RSTREAM>,
|
||||
spi: Option<SPI>,
|
||||
tx_int: TSTREAM::Interrupt,
|
||||
rx_int: RSTREAM::Interrupt,
|
||||
spi_int: SPI::Interrupt,
|
||||
channel: PhantomData<CHANNEL>,
|
||||
}
|
||||
|
||||
impl<SPI, TSTREAM, RSTREAM, CHANNEL> Spi<SPI, TSTREAM, RSTREAM, CHANNEL>
|
||||
where
|
||||
SPI: Instance
|
||||
+ PeriAddress<MemSize = u8>
|
||||
+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
|
||||
+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
|
||||
+ WithInterrupt,
|
||||
TSTREAM: Stream + WithInterrupt,
|
||||
RSTREAM: Stream + WithInterrupt,
|
||||
CHANNEL: Channel,
|
||||
{
|
||||
// Leaking futures is forbidden!
|
||||
pub unsafe fn new<PINS>(
|
||||
spi: SPI,
|
||||
streams: (TSTREAM, RSTREAM),
|
||||
pins: PINS,
|
||||
tx_int: TSTREAM::Interrupt,
|
||||
rx_int: RSTREAM::Interrupt,
|
||||
spi_int: SPI::Interrupt,
|
||||
mode: Mode,
|
||||
freq: Hertz,
|
||||
clocks: Clocks,
|
||||
) -> Self
|
||||
where
|
||||
PINS: Pins<SPI>,
|
||||
{
|
||||
let (tx_stream, rx_stream) = streams;
|
||||
|
||||
// let spi1: crate::pac::SPI1 = unsafe { mem::transmute(()) };
|
||||
// let mut hspi = crate::hal::spi::Spi::spi1(
|
||||
// spi1,
|
||||
// (
|
||||
// crate::hal::spi::NoSck,
|
||||
// crate::hal::spi::NoMiso,
|
||||
// crate::hal::spi::NoMosi,
|
||||
// ),
|
||||
// mode,
|
||||
// freq,
|
||||
// clocks,
|
||||
// );
|
||||
|
||||
unsafe { SPI::enable_clock() };
|
||||
|
||||
let clock = SPI::clock_speed(clocks);
|
||||
|
||||
// disable SS output
|
||||
// spi.cr2
|
||||
// .write(|w| w.ssoe().clear_bit().rxdmaen().set_bit().txdmaen().set_bit());
|
||||
spi.cr2.write(|w| w.ssoe().clear_bit());
|
||||
|
||||
let br = match clock.0 / freq.0 {
|
||||
0 => unreachable!(),
|
||||
1..=2 => 0b000,
|
||||
3..=5 => 0b001,
|
||||
6..=11 => 0b010,
|
||||
12..=23 => 0b011,
|
||||
24..=47 => 0b100,
|
||||
48..=95 => 0b101,
|
||||
96..=191 => 0b110,
|
||||
_ => 0b111,
|
||||
};
|
||||
|
||||
// mstr: master configuration
|
||||
// lsbfirst: MSB first
|
||||
// ssm: enable software slave management (NSS pin free for other uses)
|
||||
// ssi: set nss high = master mode
|
||||
// dff: 8 bit frames
|
||||
// bidimode: 2-line unidirectional
|
||||
// spe: enable the SPI bus
|
||||
spi.cr1.write(|w| {
|
||||
w.cpha()
|
||||
.bit(mode.phase == Phase::CaptureOnSecondTransition)
|
||||
.cpol()
|
||||
.bit(mode.polarity == Polarity::IdleHigh)
|
||||
.mstr()
|
||||
.set_bit()
|
||||
.br()
|
||||
.bits(br)
|
||||
.lsbfirst()
|
||||
.clear_bit()
|
||||
.ssm()
|
||||
.set_bit()
|
||||
.ssi()
|
||||
.set_bit()
|
||||
.rxonly()
|
||||
.clear_bit()
|
||||
.dff()
|
||||
.clear_bit()
|
||||
.bidimode()
|
||||
.clear_bit()
|
||||
.spe()
|
||||
.set_bit()
|
||||
});
|
||||
|
||||
Self {
|
||||
tx_stream: Some(tx_stream),
|
||||
rx_stream: Some(rx_stream),
|
||||
spi: Some(spi),
|
||||
tx_int: tx_int,
|
||||
rx_int: rx_int,
|
||||
spi_int: spi_int,
|
||||
channel: PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<SPI, TSTREAM, RSTREAM, CHANNEL> FullDuplex<u8> for Spi<SPI, TSTREAM, RSTREAM, CHANNEL>
|
||||
where
|
||||
SPI: Instance
|
||||
+ PeriAddress<MemSize = u8>
|
||||
+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
|
||||
+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
|
||||
+ WithInterrupt
|
||||
+ 'static,
|
||||
TSTREAM: Stream + WithInterrupt + 'static,
|
||||
RSTREAM: Stream + WithInterrupt + 'static,
|
||||
CHANNEL: Channel + 'static,
|
||||
{
|
||||
type Error = Error;
|
||||
|
||||
type WriteFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
|
||||
type ReadFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
|
||||
type WriteReadFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
|
||||
|
||||
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
||||
#[allow(mutable_transmutes)]
|
||||
let static_buf: &'static mut [u8] = unsafe { mem::transmute(buf) };
|
||||
|
||||
async move {
|
||||
let rx_stream = self.rx_stream.take().unwrap();
|
||||
let spi = self.spi.take().unwrap();
|
||||
|
||||
spi.cr2.modify(|_, w| w.errie().set_bit());
|
||||
|
||||
let mut rx_transfer = Transfer::init(
|
||||
rx_stream,
|
||||
spi,
|
||||
static_buf,
|
||||
None,
|
||||
DmaConfig::default()
|
||||
.transfer_complete_interrupt(true)
|
||||
.memory_increment(true)
|
||||
.double_buffer(false),
|
||||
);
|
||||
|
||||
let fut = InterruptFuture::new(&mut self.rx_int);
|
||||
let fut_err = InterruptFuture::new(&mut self.spi_int);
|
||||
|
||||
rx_transfer.start(|_spi| {});
|
||||
future::select(fut, fut_err).await;
|
||||
|
||||
let (rx_stream, spi, _buf, _) = rx_transfer.free();
|
||||
|
||||
spi.cr2.modify(|_, w| w.errie().clear_bit());
|
||||
self.rx_stream.replace(rx_stream);
|
||||
self.spi.replace(spi);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
||||
#[allow(mutable_transmutes)]
|
||||
let static_buf: &'static mut [u8] = unsafe { mem::transmute(buf) };
|
||||
|
||||
async move {
|
||||
let tx_stream = self.tx_stream.take().unwrap();
|
||||
let spi = self.spi.take().unwrap();
|
||||
|
||||
spi.cr2
|
||||
.modify(|_, w| w.errie().set_bit().txeie().set_bit().rxneie().set_bit());
|
||||
|
||||
// let mut tx_transfer = Transfer::init(
|
||||
// tx_stream,
|
||||
// spi,
|
||||
// static_buf,
|
||||
// None,
|
||||
// DmaConfig::default()
|
||||
// .transfer_complete_interrupt(true)
|
||||
// .memory_increment(true)
|
||||
// .double_buffer(false),
|
||||
// );
|
||||
//
|
||||
// let fut = InterruptFuture::new(&mut self.tx_int);
|
||||
//
|
||||
// tx_transfer.start(|_spi| {});
|
||||
// fut.await;
|
||||
|
||||
// let (tx_stream, spi, _buf, _) = tx_transfer.free();
|
||||
|
||||
for i in 0..(static_buf.len() - 1) {
|
||||
let byte = static_buf[i];
|
||||
loop {
|
||||
match write_sr(&spi, byte) {
|
||||
Ok(()) => break,
|
||||
_ => {}
|
||||
}
|
||||
InterruptFuture::new(&mut self.spi_int).await;
|
||||
}
|
||||
}
|
||||
|
||||
spi.cr2.modify(|_, w| {
|
||||
w.errie()
|
||||
.clear_bit()
|
||||
.txeie()
|
||||
.clear_bit()
|
||||
.rxneie()
|
||||
.clear_bit()
|
||||
});
|
||||
self.tx_stream.replace(tx_stream);
|
||||
self.spi.replace(spi);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
fn read_write<'a>(
|
||||
&'a mut self,
|
||||
read_buf: &'a mut [u8],
|
||||
write_buf: &'a [u8],
|
||||
) -> Self::WriteReadFuture<'a> {
|
||||
#[allow(mutable_transmutes)]
|
||||
let write_static_buf: &'static mut [u8] = unsafe { mem::transmute(write_buf) };
|
||||
let read_static_buf: &'static mut [u8] = unsafe { mem::transmute(read_buf) };
|
||||
|
||||
async move {
|
||||
let tx_stream = self.tx_stream.take().unwrap();
|
||||
let rx_stream = self.rx_stream.take().unwrap();
|
||||
let spi_tx = self.spi.take().unwrap();
|
||||
let spi_rx: SPI = unsafe { mem::transmute_copy(&spi_tx) };
|
||||
|
||||
spi_rx
|
||||
.cr2
|
||||
.modify(|_, w| w.errie().set_bit().txeie().set_bit().rxneie().set_bit());
|
||||
|
||||
// let mut tx_transfer = Transfer::init(
|
||||
// tx_stream,
|
||||
// spi_tx,
|
||||
// write_static_buf,
|
||||
// None,
|
||||
// DmaConfig::default()
|
||||
// .transfer_complete_interrupt(true)
|
||||
// .memory_increment(true)
|
||||
// .double_buffer(false),
|
||||
// );
|
||||
//
|
||||
// let mut rx_transfer = Transfer::init(
|
||||
// rx_stream,
|
||||
// spi_rx,
|
||||
// read_static_buf,
|
||||
// None,
|
||||
// DmaConfig::default()
|
||||
// .transfer_complete_interrupt(true)
|
||||
// .memory_increment(true)
|
||||
// .double_buffer(false),
|
||||
// );
|
||||
//
|
||||
// let tx_fut = InterruptFuture::new(&mut self.tx_int);
|
||||
// let rx_fut = InterruptFuture::new(&mut self.rx_int);
|
||||
// let rx_fut_err = InterruptFuture::new(&mut self.spi_int);
|
||||
//
|
||||
// rx_transfer.start(|_spi| {});
|
||||
// tx_transfer.start(|_spi| {});
|
||||
//
|
||||
// time::Timer::after(time::Duration::from_millis(500)).await;
|
||||
//
|
||||
// // tx_fut.await;
|
||||
// // future::select(rx_fut, rx_fut_err).await;
|
||||
//
|
||||
// let (rx_stream, spi_rx, _buf, _) = rx_transfer.free();
|
||||
// let (tx_stream, _, _buf, _) = tx_transfer.free();
|
||||
|
||||
for i in 0..(read_static_buf.len() - 1) {
|
||||
let byte = write_static_buf[i];
|
||||
loop {
|
||||
let fut = InterruptFuture::new(&mut self.spi_int);
|
||||
match write_sr(&spi_tx, byte) {
|
||||
Ok(()) => break,
|
||||
_ => {}
|
||||
}
|
||||
fut.await;
|
||||
}
|
||||
|
||||
loop {
|
||||
let fut = InterruptFuture::new(&mut self.spi_int);
|
||||
match read_sr(&spi_tx) {
|
||||
Ok(byte) => {
|
||||
read_static_buf[i] = byte;
|
||||
break;
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
fut.await;
|
||||
}
|
||||
}
|
||||
|
||||
spi_rx.cr2.modify(|_, w| {
|
||||
w.errie()
|
||||
.clear_bit()
|
||||
.txeie()
|
||||
.clear_bit()
|
||||
.rxneie()
|
||||
.clear_bit()
|
||||
});
|
||||
self.rx_stream.replace(rx_stream);
|
||||
self.tx_stream.replace(tx_stream);
|
||||
self.spi.replace(spi_rx);
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mod private {
|
||||
pub trait Sealed {}
|
||||
}
|
||||
|
||||
pub trait WithInterrupt: private::Sealed {
|
||||
type Interrupt: Interrupt;
|
||||
}
|
||||
|
||||
pub trait Instance: Deref<Target = pac::spi1::RegisterBlock> + private::Sealed {
|
||||
unsafe fn enable_clock();
|
||||
fn clock_speed(clocks: Clocks) -> Hertz;
|
||||
}
|
||||
|
||||
macro_rules! dma {
|
||||
($($PER:ident => ($dma:ident, $stream:ident),)+) => {
|
||||
$(
|
||||
impl private::Sealed for dma::$stream<pac::$dma> {}
|
||||
impl WithInterrupt for dma::$stream<pac::$dma> {
|
||||
type Interrupt = interrupt::$PER;
|
||||
}
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
||||
macro_rules! spi {
|
||||
($($PER:ident => ($SPI:ident, $pclkX:ident, $apbXenr:ident, $en:expr),)+) => {
|
||||
$(
|
||||
impl private::Sealed for pac::$SPI {}
|
||||
impl Instance for pac::$SPI {
|
||||
unsafe fn enable_clock() {
|
||||
const EN_BIT: u8 = $en;
|
||||
// NOTE(unsafe) self reference will only be used for atomic writes with no side effects.
|
||||
let rcc = &(*pac::RCC::ptr());
|
||||
// Enable clock.
|
||||
bb::set(&rcc.$apbXenr, EN_BIT);
|
||||
// Stall the pipeline to work around erratum 2.1.13 (DM00037591)
|
||||
cortex_m::asm::dsb();
|
||||
}
|
||||
|
||||
fn clock_speed(clocks: Clocks) -> Hertz {
|
||||
clocks.$pclkX()
|
||||
}
|
||||
}
|
||||
impl WithInterrupt for pac::$SPI {
|
||||
type Interrupt = interrupt::$PER;
|
||||
}
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
||||
dma! {
|
||||
DMA2_STREAM0 => (DMA2, Stream0),
|
||||
DMA2_STREAM1 => (DMA2, Stream1),
|
||||
DMA2_STREAM2 => (DMA2, Stream2),
|
||||
DMA2_STREAM3 => (DMA2, Stream3),
|
||||
DMA2_STREAM4 => (DMA2, Stream4),
|
||||
DMA2_STREAM5 => (DMA2, Stream5),
|
||||
DMA2_STREAM6 => (DMA2, Stream6),
|
||||
DMA2_STREAM7 => (DMA2, Stream7),
|
||||
DMA1_STREAM0 => (DMA1, Stream0),
|
||||
DMA1_STREAM1 => (DMA1, Stream1),
|
||||
DMA1_STREAM2 => (DMA1, Stream2),
|
||||
DMA1_STREAM3 => (DMA1, Stream3),
|
||||
DMA1_STREAM4 => (DMA1, Stream4),
|
||||
DMA1_STREAM5 => (DMA1, Stream5),
|
||||
DMA1_STREAM6 => (DMA1, Stream6),
|
||||
}
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f446",
|
||||
))]
|
||||
spi! {
|
||||
SPI1 => (SPI1, pclk2, apb2enr, 12),
|
||||
SPI2 => (SPI2, pclk1, apb2enr, 14),
|
||||
// SPI6 => (SPI6, pclk2, apb2enr, 21),
|
||||
SPI4 => (SPI3, pclk2, apb2enr, 13),
|
||||
// SPI5 => (SPI3, pclk2, apb2enr, 20),
|
||||
}
|
||||
|
||||
#[cfg(any(feature = "stm32f405", feature = "stm32f407"))]
|
||||
spi! {
|
||||
SPI1 => (SPI1, pclk2, apb2enr, 12),
|
||||
SPI3 => (SPI3, pclk1, apb2enr, 15),
|
||||
}
|
||||
@ -1,61 +0,0 @@
|
||||
use crate::{hal::prelude::*, pac, Peripherals};
|
||||
|
||||
#[derive(Default)]
|
||||
pub struct Config {
|
||||
pub use_hse: Option<u32>,
|
||||
pub sysclk: Option<u32>,
|
||||
pub pclk1: Option<u32>,
|
||||
pub require_pll48clk: bool,
|
||||
}
|
||||
|
||||
impl Config {
|
||||
pub fn new() -> Self {
|
||||
Default::default()
|
||||
}
|
||||
|
||||
pub fn use_hse(mut self, freq: u32) -> Self {
|
||||
self.use_hse = Some(freq);
|
||||
self
|
||||
}
|
||||
|
||||
pub fn sysclk(mut self, freq: u32) -> Self {
|
||||
self.sysclk = Some(freq);
|
||||
self
|
||||
}
|
||||
|
||||
pub fn pclk1(mut self, freq: u32) -> Self {
|
||||
self.pclk1 = Some(freq);
|
||||
self
|
||||
}
|
||||
|
||||
pub fn require_pll48clk(mut self) -> Self {
|
||||
self.require_pll48clk = true;
|
||||
self
|
||||
}
|
||||
}
|
||||
|
||||
/// safety: must only call once.
|
||||
pub unsafe fn configure(config: Config) {
|
||||
let dp = pac::Peripherals::take().unwrap();
|
||||
let mut cfgr = dp.RCC.constrain().cfgr;
|
||||
|
||||
if let Some(hz) = config.use_hse {
|
||||
cfgr = cfgr.use_hse(hz.mhz());
|
||||
};
|
||||
|
||||
if let Some(hz) = config.sysclk {
|
||||
cfgr = cfgr.sysclk(hz.mhz());
|
||||
};
|
||||
|
||||
if let Some(hz) = config.pclk1 {
|
||||
cfgr = cfgr.pclk1(hz.mhz());
|
||||
};
|
||||
|
||||
if config.require_pll48clk {
|
||||
cfgr = cfgr.require_pll48clk();
|
||||
};
|
||||
|
||||
let clocks = cfgr.freeze();
|
||||
|
||||
unsafe { Peripherals::set_peripherals(clocks) };
|
||||
}
|
||||
@ -1,114 +0,0 @@
|
||||
#![macro_use]
|
||||
#![allow(clippy::module_inception)]
|
||||
#![allow(unused)]
|
||||
|
||||
#[cfg(all(feature = "defmt", feature = "log"))]
|
||||
compile_error!("You may not enable both `defmt` and `log` features.");
|
||||
|
||||
pub use fmt::*;
|
||||
|
||||
#[cfg(feature = "defmt")]
|
||||
mod fmt {
|
||||
pub use defmt::{
|
||||
assert, assert_eq, assert_ne, debug, debug_assert, debug_assert_eq, debug_assert_ne, error,
|
||||
info, panic, todo, trace, unreachable, unwrap, warn,
|
||||
};
|
||||
}
|
||||
|
||||
#[cfg(feature = "log")]
|
||||
mod fmt {
|
||||
pub use core::{
|
||||
assert, assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, panic, todo,
|
||||
unreachable,
|
||||
};
|
||||
pub use log::{debug, error, info, trace, warn};
|
||||
}
|
||||
|
||||
#[cfg(not(any(feature = "defmt", feature = "log")))]
|
||||
mod fmt {
|
||||
#![macro_use]
|
||||
|
||||
pub use core::{
|
||||
assert, assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, panic, todo,
|
||||
unreachable,
|
||||
};
|
||||
|
||||
macro_rules! trace {
|
||||
($($msg:expr),+ $(,)?) => {
|
||||
()
|
||||
};
|
||||
}
|
||||
|
||||
macro_rules! debug {
|
||||
($($msg:expr),+ $(,)?) => {
|
||||
()
|
||||
};
|
||||
}
|
||||
|
||||
macro_rules! info {
|
||||
($($msg:expr),+ $(,)?) => {
|
||||
()
|
||||
};
|
||||
}
|
||||
|
||||
macro_rules! warn {
|
||||
($($msg:expr),+ $(,)?) => {
|
||||
()
|
||||
};
|
||||
}
|
||||
|
||||
macro_rules! error {
|
||||
($($msg:expr),+ $(,)?) => {
|
||||
()
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(not(feature = "defmt"))]
|
||||
macro_rules! unwrap {
|
||||
($arg:expr) => {
|
||||
match $crate::fmt::Try::into_result($arg) {
|
||||
::core::result::Result::Ok(t) => t,
|
||||
::core::result::Result::Err(e) => {
|
||||
::core::panic!("unwrap of `{}` failed: {:?}", ::core::stringify!($arg), e);
|
||||
}
|
||||
}
|
||||
};
|
||||
($arg:expr, $($msg:expr),+ $(,)? ) => {
|
||||
match $crate::fmt::Try::into_result($arg) {
|
||||
::core::result::Result::Ok(t) => t,
|
||||
::core::result::Result::Err(e) => {
|
||||
::core::panic!("unwrap of `{}` failed: {}: {:?}", ::core::stringify!($arg), ::core::format_args!($($msg,)*), e);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
|
||||
pub struct NoneError;
|
||||
|
||||
pub trait Try {
|
||||
type Ok;
|
||||
type Error;
|
||||
fn into_result(self) -> Result<Self::Ok, Self::Error>;
|
||||
}
|
||||
|
||||
impl<T> Try for Option<T> {
|
||||
type Ok = T;
|
||||
type Error = NoneError;
|
||||
|
||||
#[inline]
|
||||
fn into_result(self) -> Result<T, NoneError> {
|
||||
self.ok_or(NoneError)
|
||||
}
|
||||
}
|
||||
|
||||
impl<T, E> Try for Result<T, E> {
|
||||
type Ok = T;
|
||||
type Error = E;
|
||||
|
||||
#[inline]
|
||||
fn into_result(self) -> Self {
|
||||
self
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,2 +0,0 @@
|
||||
pub mod rtc;
|
||||
pub mod system;
|
||||
@ -1,372 +0,0 @@
|
||||
use crate::hal::rcc::Clocks;
|
||||
use atomic_polyfill::{compiler_fence, AtomicU32, Ordering};
|
||||
use core::cell::Cell;
|
||||
use core::convert::TryInto;
|
||||
use critical_section::CriticalSection;
|
||||
use embassy::interrupt::InterruptExt;
|
||||
use embassy::time::{Clock, TICKS_PER_SECOND};
|
||||
use embassy::util::CriticalSectionMutex as Mutex;
|
||||
|
||||
use crate::interrupt;
|
||||
use crate::interrupt::Interrupt;
|
||||
|
||||
// RTC timekeeping works with something we call "periods", which are time intervals
|
||||
// of 2^15 ticks. The RTC counter value is 16 bits, so one "overflow cycle" is 2 periods.
|
||||
//
|
||||
// A `period` count is maintained in parallel to the RTC hardware `counter`, like this:
|
||||
// - `period` and `counter` start at 0
|
||||
// - `period` is incremented on overflow (at counter value 0)
|
||||
// - `period` is incremented "midway" between overflows (at counter value 0x8000)
|
||||
//
|
||||
// Therefore, when `period` is even, counter is in 0..0x7FFF. When odd, counter is in 0x8000..0xFFFF
|
||||
// This allows for now() to return the correct value even if it races an overflow.
|
||||
//
|
||||
// To get `now()`, `period` is read first, then `counter` is read. If the counter value matches
|
||||
// the expected range for the `period` parity, we're done. If it doesn't, this means that
|
||||
// a new period start has raced us between reading `period` and `counter`, so we assume the `counter` value
|
||||
// corresponds to the next period.
|
||||
//
|
||||
// `period` is a 32bit integer, so It overflows on 2^32 * 2^15 / 32768 seconds of uptime, which is 136 years.
|
||||
fn calc_now(period: u32, counter: u16) -> u64 {
|
||||
((period as u64) << 15) + ((counter as u32 ^ ((period & 1) << 15)) as u64)
|
||||
}
|
||||
|
||||
struct AlarmState {
|
||||
timestamp: Cell<u64>,
|
||||
callback: Cell<Option<(fn(*mut ()), *mut ())>>,
|
||||
}
|
||||
|
||||
impl AlarmState {
|
||||
fn new() -> Self {
|
||||
Self {
|
||||
timestamp: Cell::new(u64::MAX),
|
||||
callback: Cell::new(None),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// TODO: This is sometimes wasteful, try to find a better way
|
||||
const ALARM_COUNT: usize = 3;
|
||||
|
||||
/// RTC timer that can be used by the executor and to set alarms.
|
||||
///
|
||||
/// It can work with Timers 2 and 3.
|
||||
|
||||
/// This timer works internally with a unit of 2^15 ticks, which means that if a call to
|
||||
/// [`embassy::time::Clock::now`] is blocked for that amount of ticks the returned value will be
|
||||
/// wrong (an old value). The current default tick rate is 32768 ticks per second.
|
||||
pub struct RTC<T: Instance> {
|
||||
rtc: T,
|
||||
irq: T::Interrupt,
|
||||
|
||||
/// Number of 2^23 periods elapsed since boot.
|
||||
period: AtomicU32,
|
||||
|
||||
/// Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled.
|
||||
alarms: Mutex<[AlarmState; ALARM_COUNT]>,
|
||||
|
||||
clocks: Clocks,
|
||||
}
|
||||
|
||||
impl<T: Instance> RTC<T> {
|
||||
pub fn new(rtc: T, irq: T::Interrupt, clocks: Clocks) -> Self {
|
||||
Self {
|
||||
rtc,
|
||||
irq,
|
||||
period: AtomicU32::new(0),
|
||||
alarms: Mutex::new([AlarmState::new(), AlarmState::new(), AlarmState::new()]),
|
||||
clocks,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn start(&'static self) {
|
||||
self.rtc.enable_clock();
|
||||
self.rtc.stop_and_reset();
|
||||
|
||||
let freq = T::pclk(&self.clocks);
|
||||
let psc = freq / TICKS_PER_SECOND as u32 - 1;
|
||||
let psc: u16 = psc.try_into().unwrap();
|
||||
|
||||
self.rtc.set_psc_arr(psc, u16::MAX);
|
||||
// Mid-way point
|
||||
self.rtc.set_compare(0, 0x8000);
|
||||
self.rtc.set_compare_interrupt(0, true);
|
||||
|
||||
self.irq.set_handler(|ptr| unsafe {
|
||||
let this = &*(ptr as *const () as *const Self);
|
||||
this.on_interrupt();
|
||||
});
|
||||
self.irq.set_handler_context(self as *const _ as *mut _);
|
||||
self.irq.unpend();
|
||||
self.irq.enable();
|
||||
|
||||
self.rtc.start();
|
||||
}
|
||||
|
||||
fn on_interrupt(&self) {
|
||||
if self.rtc.overflow_interrupt_status() {
|
||||
self.rtc.overflow_clear_flag();
|
||||
self.next_period();
|
||||
}
|
||||
|
||||
// Half overflow
|
||||
if self.rtc.compare_interrupt_status(0) {
|
||||
self.rtc.compare_clear_flag(0);
|
||||
self.next_period();
|
||||
}
|
||||
|
||||
for n in 1..=ALARM_COUNT {
|
||||
if self.rtc.compare_interrupt_status(n) {
|
||||
self.rtc.compare_clear_flag(n);
|
||||
critical_section::with(|cs| self.trigger_alarm(n, cs));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn next_period(&self) {
|
||||
critical_section::with(|cs| {
|
||||
let period = self.period.fetch_add(1, Ordering::Relaxed) + 1;
|
||||
let t = (period as u64) << 15;
|
||||
|
||||
for n in 1..=ALARM_COUNT {
|
||||
let alarm = &self.alarms.borrow(cs)[n - 1];
|
||||
let at = alarm.timestamp.get();
|
||||
|
||||
let diff = at - t;
|
||||
if diff < 0xc000 {
|
||||
self.rtc.set_compare(n, at as u16);
|
||||
self.rtc.set_compare_interrupt(n, true);
|
||||
}
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
fn trigger_alarm(&self, n: usize, cs: CriticalSection) {
|
||||
self.rtc.set_compare_interrupt(n, false);
|
||||
|
||||
let alarm = &self.alarms.borrow(cs)[n - 1];
|
||||
alarm.timestamp.set(u64::MAX);
|
||||
|
||||
// Call after clearing alarm, so the callback can set another alarm.
|
||||
if let Some((f, ctx)) = alarm.callback.get() {
|
||||
f(ctx);
|
||||
}
|
||||
}
|
||||
|
||||
fn set_alarm_callback(&self, n: usize, callback: fn(*mut ()), ctx: *mut ()) {
|
||||
critical_section::with(|cs| {
|
||||
let alarm = &self.alarms.borrow(cs)[n - 1];
|
||||
alarm.callback.set(Some((callback, ctx)));
|
||||
})
|
||||
}
|
||||
|
||||
fn set_alarm(&self, n: usize, timestamp: u64) {
|
||||
critical_section::with(|cs| {
|
||||
let alarm = &self.alarms.borrow(cs)[n - 1];
|
||||
alarm.timestamp.set(timestamp);
|
||||
|
||||
let t = self.now();
|
||||
if timestamp <= t {
|
||||
self.trigger_alarm(n, cs);
|
||||
return;
|
||||
}
|
||||
|
||||
let diff = timestamp - t;
|
||||
if diff < 0xc000 {
|
||||
let safe_timestamp = timestamp.max(t + 3);
|
||||
self.rtc.set_compare(n, safe_timestamp as u16);
|
||||
self.rtc.set_compare_interrupt(n, true);
|
||||
} else {
|
||||
self.rtc.set_compare_interrupt(n, false);
|
||||
}
|
||||
});
|
||||
}
|
||||
|
||||
pub fn alarm1(&'static self) -> Alarm<T> {
|
||||
Alarm { n: 1, rtc: self }
|
||||
}
|
||||
pub fn alarm2(&'static self) -> Option<Alarm<T>> {
|
||||
if T::REAL_ALARM_COUNT >= 2 {
|
||||
Some(Alarm { n: 2, rtc: self })
|
||||
} else {
|
||||
None
|
||||
}
|
||||
}
|
||||
pub fn alarm3(&'static self) -> Option<Alarm<T>> {
|
||||
if T::REAL_ALARM_COUNT >= 3 {
|
||||
Some(Alarm { n: 3, rtc: self })
|
||||
} else {
|
||||
None
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<T: Instance> embassy::time::Clock for RTC<T> {
|
||||
fn now(&self) -> u64 {
|
||||
let period = self.period.load(Ordering::Relaxed);
|
||||
compiler_fence(Ordering::Acquire);
|
||||
let counter = self.rtc.counter();
|
||||
calc_now(period, counter)
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Alarm<T: Instance> {
|
||||
n: usize,
|
||||
rtc: &'static RTC<T>,
|
||||
}
|
||||
|
||||
impl<T: Instance> embassy::time::Alarm for Alarm<T> {
|
||||
fn set_callback(&self, callback: fn(*mut ()), ctx: *mut ()) {
|
||||
self.rtc.set_alarm_callback(self.n, callback, ctx);
|
||||
}
|
||||
|
||||
fn set(&self, timestamp: u64) {
|
||||
self.rtc.set_alarm(self.n, timestamp);
|
||||
}
|
||||
|
||||
fn clear(&self) {
|
||||
self.rtc.set_alarm(self.n, u64::MAX);
|
||||
}
|
||||
}
|
||||
|
||||
mod sealed {
|
||||
pub trait Sealed {}
|
||||
}
|
||||
|
||||
pub trait Instance: sealed::Sealed + Sized + 'static {
|
||||
type Interrupt: Interrupt;
|
||||
const REAL_ALARM_COUNT: usize;
|
||||
|
||||
fn enable_clock(&self);
|
||||
fn set_compare(&self, n: usize, value: u16);
|
||||
fn set_compare_interrupt(&self, n: usize, enable: bool);
|
||||
fn compare_interrupt_status(&self, n: usize) -> bool;
|
||||
fn compare_clear_flag(&self, n: usize);
|
||||
fn overflow_interrupt_status(&self) -> bool;
|
||||
fn overflow_clear_flag(&self);
|
||||
// This method should ensure that the values are really updated before returning
|
||||
fn set_psc_arr(&self, psc: u16, arr: u16);
|
||||
fn stop_and_reset(&self);
|
||||
fn start(&self);
|
||||
fn counter(&self) -> u16;
|
||||
fn pclk(clocks: &Clocks) -> u32;
|
||||
}
|
||||
|
||||
#[allow(unused_macros)]
|
||||
macro_rules! impl_timer {
|
||||
($module:ident: ($TYPE:ident, $INT:ident, $timXen:ident, $timXrst:ident, $apbenr:ident, $apbrstr:ident, $pclk: ident)) => {
|
||||
mod $module {
|
||||
use super::*;
|
||||
use crate::hal::pac::{$TYPE, RCC};
|
||||
|
||||
impl sealed::Sealed for $TYPE {}
|
||||
|
||||
impl Instance for $TYPE {
|
||||
type Interrupt = interrupt::$INT;
|
||||
const REAL_ALARM_COUNT: usize = 3;
|
||||
|
||||
fn enable_clock(&self) {
|
||||
// NOTE(unsafe) It will only be used for atomic operations
|
||||
unsafe {
|
||||
let rcc = &*RCC::ptr();
|
||||
|
||||
rcc.$apbenr.modify(|_, w| w.$timXen().set_bit());
|
||||
rcc.$apbrstr.modify(|_, w| w.$timXrst().set_bit());
|
||||
rcc.$apbrstr.modify(|_, w| w.$timXrst().clear_bit());
|
||||
}
|
||||
}
|
||||
|
||||
fn set_compare(&self, n: usize, value: u16) {
|
||||
// NOTE(unsafe) these registers accept all the range of u16 values
|
||||
match n {
|
||||
0 => self.ccr1.write(|w| unsafe { w.bits(value.into()) }),
|
||||
1 => self.ccr2.write(|w| unsafe { w.bits(value.into()) }),
|
||||
2 => self.ccr3.write(|w| unsafe { w.bits(value.into()) }),
|
||||
3 => self.ccr4.write(|w| unsafe { w.bits(value.into()) }),
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
|
||||
fn set_compare_interrupt(&self, n: usize, enable: bool) {
|
||||
if n > 3 {
|
||||
return;
|
||||
}
|
||||
let bit = n as u8 + 1;
|
||||
unsafe {
|
||||
if enable {
|
||||
self.dier.modify(|r, w| w.bits(r.bits() | (1 << bit)));
|
||||
} else {
|
||||
self.dier.modify(|r, w| w.bits(r.bits() & !(1 << bit)));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn compare_interrupt_status(&self, n: usize) -> bool {
|
||||
let status = self.sr.read();
|
||||
match n {
|
||||
0 => status.cc1if().bit_is_set(),
|
||||
1 => status.cc2if().bit_is_set(),
|
||||
2 => status.cc3if().bit_is_set(),
|
||||
3 => status.cc4if().bit_is_set(),
|
||||
_ => false,
|
||||
}
|
||||
}
|
||||
|
||||
fn compare_clear_flag(&self, n: usize) {
|
||||
if n > 3 {
|
||||
return;
|
||||
}
|
||||
let bit = n as u8 + 1;
|
||||
unsafe {
|
||||
self.sr.modify(|r, w| w.bits(r.bits() & !(1 << bit)));
|
||||
}
|
||||
}
|
||||
|
||||
fn overflow_interrupt_status(&self) -> bool {
|
||||
self.sr.read().uif().bit_is_set()
|
||||
}
|
||||
|
||||
fn overflow_clear_flag(&self) {
|
||||
unsafe {
|
||||
self.sr.modify(|_, w| w.uif().clear_bit());
|
||||
}
|
||||
}
|
||||
|
||||
fn set_psc_arr(&self, psc: u16, arr: u16) {
|
||||
// NOTE(unsafe) All u16 values are valid
|
||||
self.psc.write(|w| unsafe { w.bits(psc.into()) });
|
||||
self.arr.write(|w| unsafe { w.bits(arr.into()) });
|
||||
|
||||
unsafe {
|
||||
// Set URS, generate update, clear URS
|
||||
self.cr1.modify(|_, w| w.urs().set_bit());
|
||||
self.egr.write(|w| w.ug().set_bit());
|
||||
self.cr1.modify(|_, w| w.urs().clear_bit());
|
||||
}
|
||||
}
|
||||
|
||||
fn stop_and_reset(&self) {
|
||||
unsafe {
|
||||
self.cr1.modify(|_, w| w.cen().clear_bit());
|
||||
}
|
||||
self.cnt.reset();
|
||||
}
|
||||
|
||||
fn start(&self) {
|
||||
self.cr1.modify(|_, w| w.cen().set_bit());
|
||||
}
|
||||
|
||||
fn counter(&self) -> u16 {
|
||||
self.cnt.read().bits() as u16
|
||||
}
|
||||
|
||||
fn pclk(clocks: &Clocks) -> u32 {
|
||||
clocks.$pclk().0
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
impl_timer!(tim2: (TIM2, TIM2, tim2en, tim2rst, apb1enr, apb1rstr, apb1_tim_clk));
|
||||
impl_timer!(tim3: (TIM3, TIM3, tim3en, tim3rst, apb1enr, apb1rstr, apb1_tim_clk));
|
||||
@ -1,17 +0,0 @@
|
||||
use crate::{hal, pac, Peripherals};
|
||||
|
||||
pub use hal::{
|
||||
prelude::*,
|
||||
rcc::{Clocks, Config},
|
||||
};
|
||||
|
||||
/// safety: must only call once.
|
||||
pub unsafe fn configure(config: Config) {
|
||||
let dp = pac::Peripherals::take().unwrap();
|
||||
|
||||
let rcc = dp.RCC.freeze(config);
|
||||
|
||||
let clocks = rcc.clocks;
|
||||
|
||||
unsafe { Peripherals::set_peripherals(clocks) };
|
||||
}
|
||||
@ -1,478 +0,0 @@
|
||||
#![no_std]
|
||||
#![feature(generic_associated_types)]
|
||||
#![feature(asm)]
|
||||
#![feature(min_type_alias_impl_trait)]
|
||||
#![feature(impl_trait_in_bindings)]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
#![allow(incomplete_features)]
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
mod f4;
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
pub use {stm32f4xx_hal as hal, stm32f4xx_hal::stm32 as pac};
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
pub use {stm32l0xx_hal as hal, stm32l0xx_hal::pac};
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
mod l0;
|
||||
|
||||
#[cfg(any(feature = "stm32l0x1", feature = "stm32l0x2", feature = "stm32l0x3",))]
|
||||
pub use l0::{rtc, system};
|
||||
|
||||
pub mod fmt;
|
||||
|
||||
pub mod exti;
|
||||
pub mod interrupt;
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
pub mod can;
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
pub use f4::{rtc, serial, spi, system};
|
||||
|
||||
#[cfg(any(
|
||||
feature = "stm32f401",
|
||||
feature = "stm32f405",
|
||||
feature = "stm32f407",
|
||||
feature = "stm32f410",
|
||||
feature = "stm32f411",
|
||||
feature = "stm32f412",
|
||||
feature = "stm32f413",
|
||||
feature = "stm32f415",
|
||||
feature = "stm32f417",
|
||||
feature = "stm32f423",
|
||||
feature = "stm32f427",
|
||||
feature = "stm32f429",
|
||||
feature = "stm32f437",
|
||||
feature = "stm32f439",
|
||||
feature = "stm32f446",
|
||||
feature = "stm32f469",
|
||||
feature = "stm32f479",
|
||||
))]
|
||||
unsafe impl embassy_extras::usb::USBInterrupt for interrupt::OTG_FS {}
|
||||
|
||||
use core::option::Option;
|
||||
use hal::prelude::*;
|
||||
use hal::rcc::Clocks;
|
||||
|
||||
#[cfg(feature = "stm32f401")]
|
||||
embassy_extras::std_peripherals! {
|
||||
ADC_COMMON,
|
||||
ADC1,
|
||||
CRC,
|
||||
DBGMCU,
|
||||
EXTI,
|
||||
FLASH,
|
||||
IWDG,
|
||||
OTG_FS_DEVICE,
|
||||
OTG_FS_GLOBAL,
|
||||
OTG_FS_HOST,
|
||||
OTG_FS_PWRCLK,
|
||||
PWR,
|
||||
//RCC,
|
||||
RTC,
|
||||
SDIO,
|
||||
SYSCFG,
|
||||
TIM1,
|
||||
TIM8,
|
||||
TIM10,
|
||||
TIM11,
|
||||
TIM2,
|
||||
//TIM3,
|
||||
TIM4,
|
||||
TIM5,
|
||||
TIM9,
|
||||
USART1,
|
||||
USART2,
|
||||
USART6,
|
||||
WWDG,
|
||||
DMA2,
|
||||
DMA1,
|
||||
GPIOH,
|
||||
GPIOE,
|
||||
GPIOD,
|
||||
GPIOC,
|
||||
GPIOB,
|
||||
GPIOA,
|
||||
I2C3,
|
||||
I2C2,
|
||||
I2C1,
|
||||
I2S2EXT,
|
||||
I2S3EXT,
|
||||
SPI1,
|
||||
SPI2,
|
||||
SPI3,
|
||||
SPI4,
|
||||
FPU,
|
||||
STK,
|
||||
NVIC_STIR,
|
||||
FPU_CPACR,
|
||||
SCB_ACTRL,
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32f446")]
|
||||
embassy_extras::std_peripherals! {
|
||||
DCMI,
|
||||
FMC,
|
||||
DBGMCU,
|
||||
DMA2,
|
||||
DMA1,
|
||||
// RCC,
|
||||
GPIOH,
|
||||
GPIOG,
|
||||
GPIOF,
|
||||
GPIOE,
|
||||
GPIOD,
|
||||
GPIOC,
|
||||
GPIOB,
|
||||
GPIOA,
|
||||
SYSCFG,
|
||||
SPI1,
|
||||
SPI2,
|
||||
SPI3,
|
||||
SPI4,
|
||||
ADC1,
|
||||
ADC2,
|
||||
ADC3,
|
||||
USART6,
|
||||
USART1,
|
||||
USART2,
|
||||
USART3,
|
||||
DAC,
|
||||
I2C3,
|
||||
I2C2,
|
||||
I2C1,
|
||||
IWDG,
|
||||
WWDG,
|
||||
RTC,
|
||||
UART4,
|
||||
UART5,
|
||||
ADC_COMMON,
|
||||
TIM1,
|
||||
TIM2,
|
||||
TIM8,
|
||||
// TIM3,
|
||||
TIM4,
|
||||
TIM5,
|
||||
TIM9,
|
||||
TIM12,
|
||||
TIM10,
|
||||
TIM13,
|
||||
TIM14,
|
||||
TIM11,
|
||||
TIM6,
|
||||
TIM7,
|
||||
CRC,
|
||||
OTG_FS_GLOBAL,
|
||||
OTG_FS_HOST,
|
||||
OTG_FS_DEVICE,
|
||||
OTG_FS_PWRCLK,
|
||||
CAN1,
|
||||
CAN2,
|
||||
FLASH,
|
||||
EXTI,
|
||||
OTG_HS_GLOBAL,
|
||||
OTG_HS_HOST,
|
||||
OTG_HS_DEVICE,
|
||||
OTG_HS_PWRCLK,
|
||||
SAI1,
|
||||
SAI2,
|
||||
PWR,
|
||||
QUADSPI,
|
||||
SPDIFRX,
|
||||
// SDMMC,
|
||||
HDMI_CEC,
|
||||
FPU,
|
||||
STK,
|
||||
NVIC_STIR,
|
||||
FPU_CPACR,
|
||||
SCB_ACTRL,
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32f405")]
|
||||
embassy_extras::std_peripherals! {
|
||||
RNG,
|
||||
DCMI,
|
||||
FSMC,
|
||||
DBGMCU,
|
||||
DMA2,
|
||||
DMA1,
|
||||
// RCC,
|
||||
GPIOI,
|
||||
GPIOH,
|
||||
GPIOG,
|
||||
GPIOF,
|
||||
GPIOE,
|
||||
GPIOD,
|
||||
GPIOC,
|
||||
GPIOJ,
|
||||
GPIOK,
|
||||
GPIOB,
|
||||
GPIOA,
|
||||
SYSCFG,
|
||||
SPI1,
|
||||
SPI2,
|
||||
SPI3,
|
||||
I2S2EXT,
|
||||
I2S3EXT,
|
||||
SPI4,
|
||||
SPI5,
|
||||
SPI6,
|
||||
SDIO,
|
||||
ADC1,
|
||||
ADC2,
|
||||
ADC3,
|
||||
USART6,
|
||||
USART1,
|
||||
USART2,
|
||||
USART3,
|
||||
DAC,
|
||||
PWR,
|
||||
I2C3,
|
||||
I2C2,
|
||||
I2C1,
|
||||
IWDG,
|
||||
WWDG,
|
||||
RTC,
|
||||
UART4,
|
||||
UART5,
|
||||
UART7,
|
||||
UART8,
|
||||
ADC_COMMON,
|
||||
TIM1,
|
||||
TIM8,
|
||||
TIM2,
|
||||
// TIM3,
|
||||
TIM4,
|
||||
TIM5,
|
||||
TIM9,
|
||||
TIM12,
|
||||
TIM10,
|
||||
TIM13,
|
||||
TIM14,
|
||||
TIM11,
|
||||
TIM6,
|
||||
TIM7,
|
||||
ETHERNET_MAC,
|
||||
ETHERNET_MMC,
|
||||
ETHERNET_PTP,
|
||||
ETHERNET_DMA,
|
||||
CRC,
|
||||
OTG_FS_GLOBAL,
|
||||
OTG_FS_HOST,
|
||||
OTG_FS_DEVICE,
|
||||
OTG_FS_PWRCLK,
|
||||
CAN1,
|
||||
CAN2,
|
||||
FLASH,
|
||||
EXTI,
|
||||
OTG_HS_GLOBAL,
|
||||
OTG_HS_HOST,
|
||||
OTG_HS_DEVICE,
|
||||
OTG_HS_PWRCLK,
|
||||
SAI1,
|
||||
LTDC,
|
||||
HASH,
|
||||
CRYP,
|
||||
FPU,
|
||||
STK,
|
||||
NVIC_STIR,
|
||||
FPU_CPACR,
|
||||
SCB_ACTRL,
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32f407")]
|
||||
embassy_extras::std_peripherals! {
|
||||
RNG,
|
||||
DCMI,
|
||||
FSMC,
|
||||
DBGMCU,
|
||||
DMA2,
|
||||
DMA1,
|
||||
// RCC,
|
||||
GPIOI,
|
||||
GPIOH,
|
||||
GPIOG,
|
||||
GPIOF,
|
||||
GPIOE,
|
||||
GPIOD,
|
||||
GPIOC,
|
||||
GPIOJ,
|
||||
GPIOK,
|
||||
GPIOB,
|
||||
GPIOA,
|
||||
SYSCFG,
|
||||
SPI1,
|
||||
SPI2,
|
||||
SPI3,
|
||||
I2S2EXT,
|
||||
I2S3EXT,
|
||||
SPI4,
|
||||
SPI5,
|
||||
SPI6,
|
||||
SDIO,
|
||||
ADC1,
|
||||
ADC2,
|
||||
ADC3,
|
||||
USART6,
|
||||
USART1,
|
||||
USART2,
|
||||
USART3,
|
||||
DAC,
|
||||
PWR,
|
||||
I2C3,
|
||||
I2C2,
|
||||
I2C1,
|
||||
IWDG,
|
||||
WWDG,
|
||||
RTC,
|
||||
UART4,
|
||||
UART5,
|
||||
UART7,
|
||||
UART8,
|
||||
ADC_COMMON,
|
||||
TIM1,
|
||||
TIM8,
|
||||
TIM2,
|
||||
// TIM3,
|
||||
TIM4,
|
||||
TIM5,
|
||||
TIM9,
|
||||
TIM12,
|
||||
TIM10,
|
||||
TIM13,
|
||||
TIM14,
|
||||
TIM11,
|
||||
TIM6,
|
||||
TIM7,
|
||||
ETHERNET_MAC,
|
||||
ETHERNET_MMC,
|
||||
ETHERNET_PTP,
|
||||
ETHERNET_DMA,
|
||||
CRC,
|
||||
OTG_FS_GLOBAL,
|
||||
OTG_FS_HOST,
|
||||
OTG_FS_DEVICE,
|
||||
OTG_FS_PWRCLK,
|
||||
CAN1,
|
||||
CAN2,
|
||||
FLASH,
|
||||
EXTI,
|
||||
OTG_HS_GLOBAL,
|
||||
OTG_HS_HOST,
|
||||
OTG_HS_DEVICE,
|
||||
OTG_HS_PWRCLK,
|
||||
SAI1,
|
||||
LTDC,
|
||||
HASH,
|
||||
CRYP,
|
||||
FPU,
|
||||
STK,
|
||||
NVIC_STIR,
|
||||
FPU_CPACR,
|
||||
SCB_ACTRL,
|
||||
}
|
||||
|
||||
#[cfg(feature = "stm32l0x2")]
|
||||
embassy_extras::std_peripherals! {
|
||||
SPI1,
|
||||
SPI2,
|
||||
USART1,
|
||||
USART2,
|
||||
USART4,
|
||||
USART5,
|
||||
I2C1,
|
||||
I2C2,
|
||||
I2C3,
|
||||
RNG,
|
||||
TIM2,
|
||||
TIM3,
|
||||
TIM6,
|
||||
TIM7,
|
||||
TIM21,
|
||||
TIM22,
|
||||
DAC,
|
||||
RTC,
|
||||
PWR,
|
||||
CRC,
|
||||
GPIOA,
|
||||
GPIOB,
|
||||
GPIOC,
|
||||
GPIOD,
|
||||
GPIOE,
|
||||
GPIOH,
|
||||
SYSCFG,
|
||||
DMA1,
|
||||
EXTI,
|
||||
ADC,
|
||||
IWDG,
|
||||
WWDG,
|
||||
DBG,
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user