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Merge pull request #1877 from xoviat/rcc

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rcc: more cleanup
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xoviat 2023-09-08 23:22:39 +00:00 committed by GitHub
commit f17f09057d
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GPG Key ID: 4AEE18F83AFDEB23
12 changed files with 79 additions and 115 deletions
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73
embassy-stm32/src/rcc/bd.rs
View File

@ -94,36 +94,49 @@ impl BackupDomain {
r
}
#[cfg(any(
rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
rtc_v3u5
))]
#[allow(dead_code, unused_variables)]
#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3))]
pub fn enable_lse(lse_drive: LseDrive) {
Self::modify(|w| {
#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
w.set_lsedrv(lse_drive.into());
w.set_lseon(true);
});
pub fn configure_ls(clock_source: RtcClockSource, lse_drive: Option<LseDrive>) {
match clock_source {
RtcClockSource::LSI => {
#[cfg(rtc_v3u5)]
let csr = crate::pac::RCC.bdcr();
while !Self::read().lserdy() {}
}
#[cfg(not(rtc_v3u5))]
let csr = crate::pac::RCC.csr();
#[allow(dead_code)]
#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3))]
pub fn enable_lsi() {
let csr = crate::pac::RCC.csr();
Self::modify(|_| {
#[cfg(not(rtc_v2wb))]
csr.modify(|w| w.set_lsion(true));
Self::modify(|_| {
#[cfg(not(rtc_v2wb))]
csr.modify(|w| w.set_lsion(true));
#[cfg(rtc_v2wb)]
csr.modify(|w| w.set_lsi1on(true));
});
#[cfg(rtc_v2wb)]
csr.modify(|w| w.set_lsi1on(true));
});
#[cfg(not(rtc_v2wb))]
while !csr.read().lsirdy() {}
#[cfg(not(rtc_v2wb))]
while !csr.read().lsirdy() {}
#[cfg(rtc_v2wb)]
while !csr.read().lsi1rdy() {}
}
RtcClockSource::LSE => {
let lse_drive = lse_drive.unwrap_or_default();
#[cfg(rtc_v2wb)]
while !csr.read().lsi1rdy() {}
Self::modify(|w| {
#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
w.set_lsedrv(lse_drive.into());
w.set_lseon(true);
});
while !Self::read().lserdy() {}
}
_ => {}
};
Self::configure_rtc(clock_source);
}
#[cfg(any(
@ -131,7 +144,7 @@ impl BackupDomain {
rtc_v3u5
))]
#[allow(dead_code, unused_variables)]
pub fn set_rtc_clock_source(clock_source: RtcClockSource) {
pub fn configure_rtc(clock_source: RtcClockSource) {
let clock_source = clock_source as u8;
#[cfg(any(
not(any(rtc_v3, rtc_v3u5, rtc_v2wb)),
@ -146,18 +159,6 @@ impl BackupDomain {
});
}
#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3))]
#[allow(dead_code, unused_variables)]
pub fn configure_rtc(clock_source: RtcClockSource, lse_drive: Option<LseDrive>) {
match clock_source {
RtcClockSource::LSI => Self::enable_lsi(),
RtcClockSource::LSE => Self::enable_lse(lse_drive.unwrap_or_default()),
_ => {}
};
Self::set_rtc_clock_source(clock_source);
}
#[cfg(any(
rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
rtc_v3u5

30
embassy-stm32/src/rcc/f2.rs
View File

@ -421,33 +421,9 @@ pub(crate) unsafe fn init(config: Config) {
RCC.apb1enr().modify(|w| w.set_pwren(true));
PWR.cr().read();
match config.rtc {
Some(RtcClockSource::LSE) => {
// 1. Unlock the backup domain
PWR.cr().modify(|w| w.set_dbp(true));
// 2. Setup the LSE
RCC.bdcr().modify(|w| {
// Enable LSE
w.set_lseon(true);
});
// Wait until LSE is running
while !RCC.bdcr().read().lserdy() {}
BackupDomain::set_rtc_clock_source(RtcClockSource::LSE);
}
Some(RtcClockSource::LSI) => {
// Turn on the internal 32 kHz LSI oscillator
RCC.csr().modify(|w| w.set_lsion(true));
// Wait until LSI is running
while !RCC.csr().read().lsirdy() {}
BackupDomain::set_rtc_clock_source(RtcClockSource::LSI);
}
_ => todo!(),
}
config
.rtc
.map(|clock_source| BackupDomain::configure_ls(clock_source, None));
set_freqs(Clocks {
sys: sys_clk,

14
embassy-stm32/src/rcc/f4.rs
View File

@ -461,17 +461,9 @@ pub(crate) unsafe fn init(config: Config) {
})
});
match config.rtc {
Some(RtcClockSource::LSI) => {
RCC.csr().modify(|w| w.set_lsion(true));
while !RCC.csr().read().lsirdy() {}
}
_ => {}
}
config.rtc.map(|clock_source| {
BackupDomain::set_rtc_clock_source(clock_source);
});
config
.rtc
.map(|clock_source| BackupDomain::configure_ls(clock_source, None));
let rtc = match config.rtc {
Some(RtcClockSource::LSI) => Some(LSI_FREQ),

2
embassy-stm32/src/rcc/l4.rs
View File

@ -407,7 +407,7 @@ pub(crate) unsafe fn init(config: Config) {
RCC.apb1enr1().modify(|w| w.set_pwren(true));
BackupDomain::configure_rtc(config.rtc_mux, None);
BackupDomain::configure_ls(config.rtc_mux, None);
let (sys_clk, sw) = match config.mux {
ClockSrc::MSI(range) => {

19
embassy-stm32/src/rcc/wb.rs
View File

@ -276,7 +276,6 @@ pub(crate) fn compute_clocks(config: &Config) -> Clocks {
}
pub(crate) fn configure_clocks(config: &Config) {
let pwr = crate::pac::PWR;
let rcc = crate::pac::RCC;
let needs_hsi = if let Some(pll_mux) = &config.mux {
@ -293,17 +292,11 @@ pub(crate) fn configure_clocks(config: &Config) {
while !rcc.cr().read().hsirdy() {}
}
match &config.lse {
Some(_) => {
rcc.cfgr().modify(|w| w.set_stopwuck(true));
rcc.cfgr().modify(|w| w.set_stopwuck(true));
pwr.cr1().modify(|w| w.set_dbp(true));
pwr.cr1().modify(|w| w.set_dbp(true));
rcc.bdcr().modify(|w| w.set_lseon(true));
}
_ => {}
}
config
.rtc
.map(|clock_source| BackupDomain::configure_ls(clock_source, None));
match &config.hse {
Some(hse) => {
@ -363,8 +356,4 @@ pub(crate) fn configure_clocks(config: &Config) {
w.set_c2hpre(config.ahb2_pre.into());
w.set_shdhpre(config.ahb3_pre.into());
});
config
.rtc
.map(|clock_source| BackupDomain::configure_rtc(clock_source, None));
}

23
embassy-stm32/src/rcc/wl.rs
View File

@ -137,8 +137,6 @@ pub struct Config {
pub shd_ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub enable_lsi: bool,
pub enable_rtc_apb: bool,
pub rtc_mux: RtcClockSource,
pub adc_clock_source: AdcClockSource,
}
@ -152,8 +150,6 @@ impl Default for Config {
shd_ahb_pre: AHBPrescaler::NotDivided,
apb1_pre: APBPrescaler::NotDivided,
apb2_pre: APBPrescaler::NotDivided,
enable_lsi: false,
enable_rtc_apb: false,
rtc_mux: RtcClockSource::LSI,
adc_clock_source: AdcClockSource::default(),
}
@ -234,7 +230,8 @@ pub(crate) unsafe fn init(config: Config) {
while FLASH.acr().read().latency() != ws {}
BackupDomain::configure_rtc(config.rtc_mux, None);
// Enables the LSI if configured
BackupDomain::configure_ls(config.rtc_mux, None);
match config.mux {
ClockSrc::HSI16 => {
@ -269,14 +266,6 @@ pub(crate) unsafe fn init(config: Config) {
}
}
if config.enable_rtc_apb {
// enable peripheral clock for communication
crate::pac::RCC.apb1enr1().modify(|w| w.set_rtcapben(true));
// read to allow the pwr clock to enable
crate::pac::PWR.cr1().read();
}
RCC.extcfgr().modify(|w| {
if config.shd_ahb_pre == AHBPrescaler::NotDivided {
w.set_shdhpre(0);
@ -301,14 +290,6 @@ pub(crate) unsafe fn init(config: Config) {
// TODO: switch voltage range
if config.enable_lsi {
let csr = RCC.csr().read();
if !csr.lsion() {
RCC.csr().modify(|w| w.set_lsion(true));
while !RCC.csr().read().lsirdy() {}
}
}
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),

2
embassy-stm32/src/rtc/mod.rs
View File

@ -268,7 +268,7 @@ pub(crate) mod sealed {
crate::pac::RTC
}
fn enable_peripheral_clk() {}
fn enable_peripheral_clk();
/// Read content of the backup register.
///

9
embassy-stm32/src/rtc/v2.rs
View File

@ -270,9 +270,18 @@ impl sealed::Instance for crate::peripherals::RTC {
}
#[cfg(any(rtc_v2f2))]
{
// enable peripheral clock for communication
crate::pac::RCC.apb1enr().modify(|w| w.set_pwren(true));
// read to allow the pwr clock to enable
crate::pac::PWR.cr().read();
}
#[cfg(any(rtc_v2f0))]
{
// enable peripheral clock for communication
crate::pac::RCC.apb1enr().modify(|w| w.set_pwren(true));
}
}
fn read_backup_register(rtc: &Rtc, register: usize) -> Option<u32> {

17
embassy-stm32/src/rtc/v3.rs
View File

@ -128,6 +128,23 @@ impl super::Rtc {
impl sealed::Instance for crate::peripherals::RTC {
const BACKUP_REGISTER_COUNT: usize = 32;
fn enable_peripheral_clk() {
#[cfg(any(rcc_wle, rcc_wl5, rcc_g4))]
{
// enable peripheral clock for communication
crate::pac::RCC.apb1enr1().modify(|w| w.set_rtcapben(true));
}
#[cfg(rcc_g0)]
{
// enable peripheral clock for communication
crate::pac::RCC.apbenr1().modify(|w| w.set_rtcapben(true));
}
// read to allow the pwr clock to enable
crate::pac::PWR.cr1().read();
}
fn read_backup_register(_rtc: &Rtc, register: usize) -> Option<u32> {
#[allow(clippy::if_same_then_else)]
if register < Self::BACKUP_REGISTER_COUNT {

2
examples/stm32wl/src/bin/lora_lorawan.rs
View File

@ -33,7 +33,7 @@ bind_interrupts!(struct Irqs{
async fn main(_spawner: Spawner) {
let mut config = embassy_stm32::Config::default();
config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE32;
config.rcc.enable_lsi = true; // enable RNG
config.rcc.rtc_mux = embassy_stm32::rcc::RtcClockSource::LSI;
let p = embassy_stm32::init(config);
pac::RCC.ccipr().modify(|w| w.set_rngsel(0b01));

2
examples/stm32wl/src/bin/random.rs
View File

@ -16,7 +16,7 @@ bind_interrupts!(struct Irqs{
async fn main(_spawner: Spawner) {
let mut config = embassy_stm32::Config::default();
config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE32;
config.rcc.enable_lsi = true; //Needed for RNG to work
config.rcc.rtc_mux = embassy_stm32::rcc::RtcClockSource::LSI;
let p = embassy_stm32::init(config);
pac::RCC.ccipr().modify(|w| {

1
examples/stm32wl/src/bin/rtc.rs
View File

@ -17,7 +17,6 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.mux = ClockSrc::HSE32;
config.rcc.rtc_mux = RtcClockSource::LSE;
config.rcc.enable_rtc_apb = true;
embassy_stm32::init(config)
};
info!("Hello World!");