Commit Graph

2527 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
a5f5c3a844 net: add functions to get current Eth and IP config 2022-05-02 16:19:34 +02:00
Dario Nieuwenhuis
e74af83681
Merge pull request #744 from danbev/waker_typo
Fix typo in waker.rs
2022-05-01 20:17:35 +02:00
Daniel Bevenius
7b04c78388 Fix typo in waker.rs 2022-05-01 19:25:45 +02:00
bors[bot]
d600f39260
Merge #743
743: Add PLL config support for F2 r=Dirbaio a=Gekkio

- minor changes to make the F2 RCC API a bit more flexible
- low-level PLL config with assertions based on datasheet specs. It shouldn't be very difficult to later add a "reverse API" where you pass the clocks you want to a function and it generates a `PLLConfig` struct for you
- PLL API tested on my custom board with 12 MHz HSE as source for PLL to generate max clocks for SYSCLK/AHB/APB/APB1/PLL48
- the example *should* work but is untested since I don't have the Nucleo board 😞 

Co-authored-by: Joonas Javanainen <joonas.javanainen@gmail.com>
2022-04-30 21:08:43 +00:00
Joonas Javanainen
e88559c5ca
Use defmt-friendly error handling 2022-04-30 11:41:17 +03:00
bors[bot]
c474682ea9
Merge #733
733: Add f107 ethernet support. r=Dirbaio a=davidlenfesty

The original driver works perfectly, the only required changes were only to clock and pin configuration.

Bits that are also present and deserve some scrutiny:
- Migrated LAN8742a driver to a generic SMI version (only *functional* difference is a couple extra status checks for the link poll, which IMO weren't great anyways (i.e. it would consider the link down if it negotiated to 10M)
- Migrated f1 RCC init to "new" style. As of creating this draft PR, it is pretty much only tested on the happy path for my specific configuration, and also needs a couple things done (calculated clock speeds are hardcoded and ADC clock isn't implemented)
- Support for v1b driver (f2 and f4) was added, but not tested.

(Made a draft PR until f4 support is verified and I finish the clock init - adding testing and at least feature parity with how it was before)

Co-authored-by: David Lenfesty <lenfesty@ualberta.ca>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-04-30 04:06:17 +00:00
Dario Nieuwenhuis
804b20c5af stm32/eth: make "ethmac" vs "eth" consistent in RCC regs. 2022-04-30 04:49:57 +02:00
David Lenfesty
bb2db2b7be Update stm32-data for new generated data 2022-04-30 04:49:56 +02:00
David Lenfesty
5e6c4ae024 embassy-stm32/eth: consolidate v1a/v1c and add v1b
The only differences between v1a and v1c were clocks and GPIO, v1b will
likely work out of the box (or simply need minor tweaks)
2022-04-30 04:49:24 +02:00
David Lenfesty
2e7b42fc5b embassy-stm32/eth: convert LAN8742 driver to generic SMI driver
SMI Ethernet PHYs all share a common base set of registers that can do
90% of all tasks. The LAN8742 driver used some vendor-specific
registers to check link negotiation status, but the need for that was
debatable, so I migrated it to a generic driver instead, anybody who
wants extra functionality can copy it and impl their own on top of it.
2022-04-30 04:49:24 +02:00
David Lenfesty
905b40e212 embassy-stm32/eth/v1a: configure pins correctly for f107
v1a works correctly!
2022-04-30 04:49:24 +02:00
David Lenfesty
0d2ef1099b initial work porting eth to f107 2022-04-30 04:49:24 +02:00
David Lenfesty
f30e5d2d3f Initial import to v1a, does not compile 2022-04-30 04:49:24 +02:00
Joonas Javanainen
1d5f9b86fb
Add PLL example for F2 2022-04-29 18:21:41 +03:00
Joonas Javanainen
07ad52162b
Add PLL config support for F2 2022-04-29 18:21:40 +03:00
Joonas Javanainen
0cfe1dc9df
Move HSE config out of main clock mux
This makes the configuration more flexible and closer to the underlying
configuration register structure. For example, we could use HSI for the
system clock, but use HSE to output a clock with MCO.
2022-04-29 17:51:18 +03:00
bors[bot]
2f43969dd4
Merge #742
742: Only 1 argument in embassy::main when there is no HAL r=Dirbaio a=jbeaurivage

There is a slight mistake in an error message from `[embassy::main]` macro. When there is no HAL specified, `main` should take only one argument.

Co-authored-by: Justin Beaurivage <justin@wearableavionics.com>
2022-04-29 14:29:26 +00:00
Justin Beaurivage
c53b2fdc05 Require 1 argument in embassy::main without HAL 2022-04-29 09:32:31 -04:00
bors[bot]
b7c510beb4
Merge #738
738: Add split method to UarteWithIdle in nrf hal r=lulf a=ZoeyR

I needed this method because I was writing a driver for the sim7000 modem. Its a line based protocol so the read until idle was very useful to me. Unfortunately unlike the primary `Uarte` struct the `UarteWithIdle` didn't have `split()`. So I added it 😄 

Co-authored-by: Zoey Riordan <zoey@dos.cafe>
2022-04-28 16:25:36 +00:00
bors[bot]
0ed4d294de
Merge #741
741: Fix linker script for nrf bootloader example r=lulf a=lulf



Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-04-28 12:38:03 +00:00
Ulf Lilleengen
b7e7211a20 Fix linker script for nrf bootloader example 2022-04-28 14:11:01 +02:00
bors[bot]
bd488ef0d5
Merge #740
740: Allow using separate page sizes for state and dfu r=lulf a=lulf

* Less generics on bootloader. Keep PAGE_SIZE as a common multiple of
DFU and ACTIVE page sizes.
* Document restriction
* Add unit tests for different page sizes

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-04-28 11:31:35 +00:00
Ulf Lilleengen
bd237a1f96 Allow using separate page sizes for state and dfu
* Less generics on bootloader. Keep PAGE_SIZE as a common multiple of
DFU and ACTIVE page sizes.
* Document restriction
* Add unit tests for different page sizes
2022-04-28 10:38:25 +02:00
bors[bot]
ba46df6825
Merge #739
739: net: Add support for packet pools with size 64 and 128 r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-04-27 19:58:42 +00:00
Matous Hybl
3a3ed27c30 net: Add support for packet pools with size 64 and 128 2022-04-27 21:27:28 +02:00
Zoey Riordan
2ebc1186e0
Add split method to UarteWithIdle 2022-04-27 20:33:41 +02:00
bors[bot]
5b3aaaaa9c
Merge #737
737: Remove unnecessary feature gating for giant transfers in DCMI r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-04-27 14:54:59 +00:00
Matous Hybl
7538f57d62 Remove unnecessary feature gating for giant transfers in DCMI 2022-04-27 16:53:20 +02:00
bors[bot]
663642eabb
Merge #724
724: STM32 Flash + Bootloader  r=Dirbaio a=lulf

Not working.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
Co-authored-by: Ulf Lilleengen <ulf.lilleengen@gmail.com>
2022-04-27 13:43:15 +00:00
Ulf Lilleengen
93c17be32e Update stm32-data branch 2022-04-27 15:18:09 +02:00
Ulf Lilleengen
da61611f8f Add bootloader to CI 2022-04-27 15:17:18 +02:00
Ulf Lilleengen
484e0acc63 Add stm32 flash + bootloader support
* Add flash drivers for L0, L1, L4, WB and WL. Not tested for WB, but
should be similar to WL.
* Add embassy-boot-stm32 for bootloading on STM32.
* Add flash examples and bootloader examples
* Update stm32-data
2022-04-27 15:17:18 +02:00
bors[bot]
9c283cd445
Merge #736
736: executor: allow Send-spawning of tasks if their args are Send. r=Dirbaio a=Dirbaio

This allows send-spawning (spawning into an executor in another thread) tasks if their args are Send. Previously this would require the entire future to be Send.

--


When send-spawning a task, we construct the future in this thread, and effectively
"send" it to the executor thread by enqueuing it in its queue. Therefore, in theory,
send-spawning should require the future `F` to be `Send`.

The problem is this is more restrictive than needed. Once the future is executing,
it is never sent to another thread. It is only sent when spawning. It should be
enough for the task's arguments to be Send. (and in practice it's super easy to
accidentally make your futures !Send, for example by holding an `Rc` or a `&RefCell` across an `.await`.)

Luckily, an `async fn` future contains just the args when freshly constructed. So, if the
args are Send, it's OK to send a !Send future, as long as we do it before first polling it.


Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-04-27 12:21:25 +00:00
Dario Nieuwenhuis
1599009a4f executor: "send-spawn is OK if the args are Send" only holds for async fn futures.
The normal `spawn()` methods can be called directly by the user, with arbitrary hand-implemented futures.
We can't enforce they're only called with `async fn` futures. Therefore, make these
require `F: Send`, and add a "private" one only for use in the macro, which can enforce it.
2022-04-27 04:56:41 +02:00
Dario Nieuwenhuis
6f6c16f449 executor: make send-spawning only require the task args to be Send, not the whole future. 2022-04-27 04:56:41 +02:00
Dario Nieuwenhuis
293f54d134 executor: add raw::TaskPool.
This simplifies the macro code a bit.
2022-04-27 04:56:41 +02:00
bors[bot]
df814f9bbd
Merge #734 #735
734: executor: Add `Spawner::for_current_executor`. r=Dirbaio a=Dirbaio

This is needed to spawn non-Send tasks in an InterruptExecutor, after the fixes in #730 .

`@matoushybl` could you check if this works for your use case?

735: stm32: add stm32u5 GPDMA, SPIv4 support, add HIL tests. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-04-26 23:32:30 +00:00
Dario Nieuwenhuis
009bb8e4e1 stm32: add stm32u5 GPDMA, SPIv4 support, add HIL tests. 2022-04-27 01:16:14 +02:00
bors[bot]
3b0200daec
Merge #731
731: Update to released lorawan crates r=Dirbaio a=lulf



Co-authored-by: Ulf Lilleengen <ulf.lilleengen@gmail.com>
2022-04-26 17:35:23 +00:00
Dario Nieuwenhuis
9e897cbea9 executor: Add Spawner::for_current_executor. 2022-04-26 19:08:18 +02:00
Ulf Lilleengen
2c0e28aa0c Update to released lorawan crates 2022-04-26 19:06:15 +02:00
bors[bot]
3131510f4c
Merge #732
732: macros: simplify task macro using "TAIT laundering". r=Dirbaio a=Dirbaio

This brings the macro to the state before the nightly update #729 #730, with a much cleaner workaround for the opaque type error, from https://github.com/rust-lang/rust/issues/96406

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-04-26 17:03:06 +00:00
Dario Nieuwenhuis
96d917992c macros: simplify task macro using "TAIT laundering". 2022-04-26 18:40:45 +02:00
bors[bot]
a39d796c3d
Merge #730
730: Executor and task macro fixes. r=Dirbaio a=Dirbaio

See individual commits.

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-04-25 20:21:32 +00:00
Dario Nieuwenhuis
2b0e8a330b examples/nrf: add self_spawn example.
This serves as a compile-test of possible typecheck loops due to
TAIT shenanigans.
2022-04-25 22:19:40 +02:00
Dario Nieuwenhuis
c4cecec10c macros: isolate the TAIT into its own mod.
This fixes type inference issues due to the TAIT's defining scope
being the whole parent mod.
2022-04-25 22:18:52 +02:00
Dario Nieuwenhuis
b27feb0619 executor: fix unsoundness in InterruptExecutor::start.
The initial closure is not actually called in the interrupt, so this is
illegally sending non-Send futures to the interrupt.

Remove the closure, and return a SendSpawner instead.
2022-04-25 22:09:04 +02:00
Dario Nieuwenhuis
52ed08cf95 executor: remove useless not_send in SendSpwaner. 2022-04-25 16:38:56 +02:00
bors[bot]
97e24b0568
Merge #716
716: Implement giant (chunked) DMA transfers r=Dirbaio a=matoushybl

There is a breaking change in the Channel trait in the method `remaining_transfers()`, this method however hasn't been used anywhere in the codebase and the return type changed from u16 to u32, so all of the previous use cases should work.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-04-25 12:32:04 +00:00
Matous Hybl
945fa0871f Implement giant (chunked) DMA transfers for DCMI. 2022-04-25 14:30:43 +02:00