Commit Graph

796 Commits

Author SHA1 Message Date
Grant Miller
efd9e18321 Fix example 2023-04-05 15:12:27 -05:00
Matthew W. Samsonoff
28b8ac4b62 Update STM32F0 ADC example to use read_internal 2023-04-05 14:34:24 -05:00
Matthew W. Samsonoff
7e9e628eb9 Add ADC example for STM32F0 2023-04-05 14:34:24 -05:00
Rasmus Melchior Jacobsen
2a49e11cb0 Align flash examples 2023-04-05 10:55:31 +02:00
Rasmus Melchior Jacobsen
57d3d4d581 Align stm32 bootloader example 2023-04-05 10:29:45 +02:00
Rasmus Melchior Jacobsen
84bfe9b8c9 Align examples with bootloader changes 2023-04-04 22:44:21 +02:00
bors[bot]
5923e143e3
Merge #1321
1321: executor: add Pender, rework Cargo features. r=Dirbaio a=Dirbaio

This introduces a `Pender` struct with enum cases for thread-mode, interrupt-mode and
custom callback executors. This avoids calls through function pointers when using only
the thread or interrupt executors. Faster, and friendlier to `cargo-call-stack`.

`embassy-executor` now has `arch-xxx` Cargo features to select the arch and to enable
the builtin executors (thread and interrupt).

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-04-04 15:50:12 +00:00
bors[bot]
143105eeb6
Merge #1313
1313: (embassy-stm32): rework bufferedUart to get rid of PeripheralMutex r=Dirbaio a=MathiasKoch

New implementation is very similar to the implementation of embassy-nrf & embassy-rp. 

Also adds embedded-hal traits to bufferedUart.

**NB**: Still needs testing on actual hardware

Co-authored-by: Mathias <mk@blackbird.online>
2023-04-04 15:14:07 +00:00
Mathieu Dupont
932b80ca8a run fmt 2023-04-03 16:52:57 +02:00
Mathieu Dupont
4ce1c5f27d Add MCO support for L4 and F4 families 2023-04-03 16:41:25 +02:00
Dario Nieuwenhuis
d3c4e4a20a executor: add Pender, rework Cargo features.
This introduces a `Pender` struct with enum cases for thread-mode, interrupt-mode and
custom callback executors. This avoids calls through function pointers when using only
the thread or interrupt executors. Faster, and friendlier to `cargo-call-stack`.

`embassy-executor` now has `arch-xxx` Cargo features to select the arch and to enable
the builtin executors (thread and interrupt).
2023-04-03 03:09:11 +02:00
Mathias
472dc6b7d1 Fix interrupt handling so it is similar to before the rework, and fix examples 2023-03-31 15:57:35 +02:00
Caleb Jamison
12d6e37b3f Example using the PIO to drive WS2812 aka Neopixel RGB leds
This example also uses a pio program compiled at runtime, rather than one built at compile time. There's no reason to do that, but it's probably useful to have an example that does this as well.
2023-03-11 02:58:28 -05:00
bors[bot]
8fd30e407c
Merge #1267
1267: macros: better validation of function signatures. r=Dirbaio a=Dirbaio

Fixes #1266

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-03-08 08:17:44 +00:00
Dario Nieuwenhuis
b2c6dc45e3 Fix examples broken by the macro fix. 2023-03-08 09:17:01 +01:00
Mehmet Ali Anil
935633c90b Merge upstream 2023-03-07 23:16:54 +01:00
Mehmet Ali Anil
bc0cb43307 Bump embedded-storage-async to 0.4 2023-03-06 22:16:36 +01:00
Dario Nieuwenhuis
5249996d28 nrf/usb: switch to new interrupt binding, fix vbus detect on nrf53. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
5913553cb1 nrf/twis: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
36319fc121 nrf/temp: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
9e58d9274c nrf/twim: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
9f5762d365 nrf/spis: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
a32e82029a nrf/spim: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
2dc5608203 nrf/saadc: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
d113fcfe32 nrf/rng: make available on all chips, use Instance trait, switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
96788ac93a nrf/qspi: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
c66b28e759 nrf/qdec: make available on all chips, use Instance trait, switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
f8f1d3bcf0 nrf/pdm: make available on all chips, use Instance trait, switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
34563b74aa nrf/i2s: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
63b75eaf64 nrf/timer: remove awaitable. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
9cf000ef4e nrf/uart: switch to new interrupt binding. 2023-03-06 00:17:51 +01:00
Dario Nieuwenhuis
bf013be9ba
Merge pull request #1232 from embassy-rs/nrf-qspi-fixes
nrf/qspi: nrf53 support, u32 addrs, remove const generic, add raw read/write.
2023-03-05 03:19:11 +01:00
Dario Nieuwenhuis
f7dfc49c5c nrf/qspi: add _raw variants of methods that don't do bounds checks.
Useful for the nRF7002, which presents as a "fake" QSPI flash, and
the "capacity" concept doesn't really apply to it.
2023-03-05 02:55:00 +01:00
Dario Nieuwenhuis
8eb8ea6174 nrf/qspi: remove FLASH_SIZE const generic param. 2023-03-05 02:33:02 +01:00
Dario Nieuwenhuis
75f69803af nrf/qspi: always use u32 for addresses. 2023-03-05 02:30:53 +01:00
Dario Nieuwenhuis
916f94b366 nrf/buffered_uarte: make available on stable. 2023-03-04 15:12:49 +01:00
Dario Nieuwenhuis
ccc224c81f nrf/buffered_uarte: remove PeripheralMutex, make it work without rts/cts.
> dirbaio: so I was checking how zephyr does UARTE RX on nRF
> dirbaio: because currently we have the ugly "restart DMA on line idle to flush it" hack
> dirbaio: because according to the docs "For each byte received over the RXD line, an RXDRDY event will be generated. This event is likely to occur before the corresponding data has been transferred to Data RAM."
> dirbaio: so as I understood it, the only way to guarantee the data is actually transferred to RAM is to stop+restart DMA
> dirbaio: well, guess what?
> dirbaio: they just count RXDRDY's, and process that amount of data without restarting DMA
> dirbaio: with a timer configured as counter https://github.com/zephyrproject-rtos/zephyr/blob/main/drivers/serial/uart_nrfx_uarte.c#L650-L692
> dirbaio: 🤔🤷⁉️
> dirbaio: someone saying you can do the "hook up rxdrdy to a counter" trick, someone else saying it's wrong 🤪 https://devzone.nordicsemi.com/f/nordic-q-a/28420/uarte-in-circular-mode

So we're going to do just that!

- BufferedUarte is lock-free now. No PeripheralMutex.
- The "restart DMA on line idle to flush it" hack is GONE. This means
  - It'll work correctly without RTS/CTS now.
  - It'll have better throughput when using RTS/CTS.
2023-03-04 15:12:49 +01:00
Dario Nieuwenhuis
c4f4aa10f9
Merge pull request #1244 from embassy-rs/interruptexecutor
cortex-m/executor: don't use the owned interrupts system.
2023-03-01 22:38:27 +01:00
Dario Nieuwenhuis
6dbb631f1e Example fixes. 2023-03-01 01:32:42 +01:00
Dario Nieuwenhuis
4dfa32b1e0 cortex-m/executor: don't use the owned interrupts system.
Preparation for #1224.
2023-02-28 23:07:20 +01:00
Dario Nieuwenhuis
bc71230cd0 examples/std: fix net running out of sockets. 2023-02-26 21:50:12 +01:00
chemicstry
42462681bd stm32/sdmmc: Implement proper clock configuration 2023-02-23 16:57:21 +02:00
Dario Nieuwenhuis
ada3d5be7c nrf: rename UARTETWISPIn -> SERIALn
The UARTETWISPIn naming is quite horrible. With the nRF53, Nordic realized this
and renamed the interrupts to SERIALn. Let's copy that for our peripheral names, in nrf53 and nrf91.
2023-02-21 22:41:23 +01:00
Dario Nieuwenhuis
13328c58d3
examples/stm32wb: do not reserve words at start of RAM.
They're used to communicate from the app to ST's OTA bootloader. See AN5247. 

This bootloader is optional, must be flashed by the user, and requires changing the FLASH start address as well, so the current memory regions still require modifications to use it. Therefore there's no point in reserving these words.

Thanks @adamgreig for investigating the purpose.
2023-02-20 01:01:01 +01:00
bors[bot]
1567e724f9
Merge #1218 #1219
1218: Lora: sx126x: Change timing window to match values found experimentally. r=Dirbaio a=CBJamo

As mentioned in #1188.

1219: stm32/sdmmc: Fix SDIOv1 writes r=Dirbaio a=chemicstry

This fixes writes on sdmmc v1 (SDIO). I'm pretty sure I tested writes in #669, but maybe I was just lucky or I just forgot.

There were two problems:
- Writes require DMA FIFO mode, otherwise SDIO FIFO is under/overrun depending on sdio/pclk2 clock ratio.
- Hardware flow control is broken for sdmmc v1 (I checked F1 and F4 erratas). This causes clock glitches above 12 MHz and results in write CRC errors.

Co-authored-by: Caleb Jamison <caleb@cbjamo.com>
Co-authored-by: chemicstry <chemicstry@gmail.com>
2023-02-19 23:01:44 +00:00
bors[bot]
4ad255b34b
Merge #1217
1217: Fix a typo in "PioPeripheral" r=Dirbaio a=SekoiaTree

Renames "PioPeripherial" to "PioPeripheral" (without the second i).

Co-authored-by: sekoia <sequoia.1009@gmail.com>
2023-02-19 22:46:57 +00:00
Dario Nieuwenhuis
272982ee54 examples/stm32wb: fix linker script.
cortex-m-rt 0.7.2 now enforces the stack is 8-byte aligned. Stack is placed
at `ORIGIN(RAM) + LENGTH(RAM)` by default, which wasn't 8-byte-aligned. See https://github.com/rust-embedded/cortex-m/discussions/469

ST trims 8 bytes from start of RAM, and uses the whole 192kb, so let's just
copy that:

bceb1dae09/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld (L48)
2023-02-19 23:02:31 +01:00
chemicstry
a53f525f51 stm32/sdmmc: Fix SDIOv1 writes 2023-02-18 01:37:06 +02:00
sekoia
e641db1f75 Fix a typo in "PioPeripheral" 2023-02-15 14:10:07 +01:00
Dario Nieuwenhuis
76642b3a3c fix h7 examples 2023-02-10 23:35:44 +01:00