Grant Miller
a13a7a6616
Replace wait_for_idle with spin_until_idle
2021-12-14 17:46:25 -06:00
Grant Miller
e75cb1a564
Regs type alias
2021-12-14 15:39:00 -06:00
Grant Miller
b06658c195
Refactor new
2021-12-14 15:39:00 -06:00
VasanthakumarV
78c5d65ca9
[lint] Add newline in pwr file
2021-12-13 18:16:58 +05:30
VasanthakumarV
3f33d307ff
[feature] Add rcc register support for F3
2021-12-13 14:50:13 +05:30
VasanthakumarV
e2c074d133
[feature] Add pwr register support for F3
2021-12-13 13:49:41 +05:30
VasanthakumarV
7733d11f90
[generate] Add stm32f3 chips to the Cargo manifest
2021-12-13 13:49:41 +05:30
huntc
45ef944457
Stm flush required implementing also, along with std alloc split
2021-12-10 15:11:41 +11:00
Matous Hybl
1dd5a71c07
Add DCMI peripheral support.
2021-12-09 12:56:39 +01:00
Dario Nieuwenhuis
4ddd23d623
stm32/usart: unify v1 and v2
2021-12-08 05:12:48 +01:00
Dario Nieuwenhuis
022c4cb739
stm32/dma: simplify impls a bit.
2021-12-08 03:30:07 +01:00
Dario Nieuwenhuis
b316d2620c
stm32/dma: improve trait docs, seal Word.
2021-12-08 03:18:15 +01:00
Dario Nieuwenhuis
6179da6b9c
stm32/dma: eagerly start transfers when calling the functions.
...
`async fn`s do nothing until polled, but we want the DMA transfer to
immediately start in this case. Drivers rely on it. Some require special
orders, such as "start DMA, start SPI, then wait for DMA" which is awkward
to do without eager start.
Also use a manually-impl'd future, this allows getting rid of the "double"
Unborrow channel clone.
2021-12-08 03:04:39 +01:00
Dario Nieuwenhuis
4e349d0f5d
stm32/dma: use the right waker slot number for DMA2 (must add 8)
2021-12-08 01:54:31 +01:00
Dario Nieuwenhuis
fd2fe62b5f
stm32/dma: rename is_stopped to is_running.
...
Note that this does NOT invert the result of `en()` because it was
wrong before.
2021-12-08 01:51:39 +01:00
Matous Hybl
b2910558d3
Refactor DMA traits.
2021-12-07 21:43:47 +01:00
Joshua Salzedo
e2719aba10
Further extend the dma channel trait
2021-12-07 21:43:47 +01:00
Joshua Salzedo
93e047ede2
cargo fmt
2021-12-07 21:43:47 +01:00
Joshua Salzedo
3411039cb9
Implement extended Channel trait to bdma.rs
2021-12-07 21:43:47 +01:00
Joshua Salzedo
2d2c6d0e01
Implement extended Channel trait to dma.rs
2021-12-07 21:43:47 +01:00
Joshua Salzedo
3272987d92
Expand channel trait
2021-12-07 21:43:47 +01:00
Ulf Lilleengen
f9ac0c8047
Add back MISO flush
2021-12-07 09:40:45 +01:00
Grant Miller
79baa04118
Implement blocking traits with a macro
2021-12-07 00:03:52 -06:00
Grant Miller
bf1f80afa1
Unify blocking trait impls
2021-12-07 00:03:52 -06:00
Grant Miller
3a17e3a2a5
Move async trait impls to mod
2021-12-07 00:03:52 -06:00
Grant Miller
20d2151b1d
check_error_flags function
2021-12-07 00:03:52 -06:00
Grant Miller
496579b48b
Move Word trait to mod
2021-12-07 00:03:52 -06:00
Grant Miller
7c78247be3
v2: set frxth and ds in new
2021-12-06 22:36:53 -06:00
Grant Miller
d76bc45e30
Move Spi drop impl to mod
2021-12-06 17:19:55 -06:00
Grant Miller
bd9e730024
Move set_word_size to mod
2021-12-06 16:47:08 -06:00
Grant Miller
a35b7d90bc
Add tx_ptr and rx_ptr methods
2021-12-06 16:33:06 -06:00
Grant Miller
a35f337bd6
Move Spi::new and Spi::compute_baud_rate to mod
2021-12-06 15:19:24 -06:00
Grant Miller
75374ce7e8
Fix ssoe in v1
2021-12-06 14:57:53 -06:00
Grant Miller
e1cccc8391
Move Spi to mod (without NoDma defaults)
2021-12-06 14:47:50 -06:00
Grant Miller
aeb69a7665
Track current word size in v2 and v3 also
2021-12-06 14:24:02 -06:00
Grant Miller
d51885c0eb
Move WordSize methods to mod
2021-12-06 14:13:25 -06:00
Grant Miller
d426caefbf
Move NoPin impls from v1 to mod
2021-12-06 14:02:21 -06:00
Ulf Lilleengen
81ec4c82fd
Flush MISO before transfer operation
2021-12-03 09:53:28 +01:00
Matous Hybl
6e0eb33ea8
Downcast timer to GP16 for time drivers.
2021-12-02 18:07:05 +01:00
Matous Hybl
f0cb77443c
Fix wrong pin configuration in STM32's SPI v3.
2021-12-01 22:18:14 +01:00
Dario Nieuwenhuis
b0fabfab5d
Update stm32-data: rcc regs info comes from yamls now.
2021-11-29 02:28:02 +01:00
Ulf Lilleengen
25b49a8a2a
Remove common clock types
...
Different STM32 RCC peripherals have different capabilities and register
values. Define types for each RCC types inside each module to ensure
full range of capabilities for each family can be used
2021-11-28 16:46:08 +01:00
Dario Nieuwenhuis
006e567716
stm32/pwm: allow using the advanced timer instances too.
2021-11-27 03:06:53 +01:00
Dario Nieuwenhuis
d7d1258411
stm32/pwm: small cleanups
2021-11-27 03:05:10 +01:00
Dario Nieuwenhuis
22fad1e7bc
stm32/pwm: impl instance/pin for all chips
2021-11-27 03:04:50 +01:00
Ben Gamari
8211d58ee2
stm32/pwm: initial commit
2021-11-27 02:50:30 +01:00
Dario Nieuwenhuis
88d4b0c00d
stm32: add stm32g4 support.
2021-11-27 02:34:23 +01:00
Ulf Lilleengen
cd9a1d547c
Ensure SPI DMA write is completed
...
Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.
2021-11-24 14:59:18 +01:00
Dario Nieuwenhuis
e187f50f4b
stm32: remove unused deps
2021-11-24 01:41:51 +01:00
Dario Nieuwenhuis
dfb6d407a1
stm32: rename core features from _cmX to -cmX, cleanup gen.
2021-11-23 23:49:06 +01:00
