Thales Fragoso
6daa55a897
eth-v2: Fix setting the registers for the descriptors
...
Also, the interrupts are set to 1 to clear, the manual could have helped
with that one...
2021-06-16 16:48:35 +02:00
Thales Fragoso
0b42e12604
eth-v2: Fix off by one bug
2021-06-16 16:48:35 +02:00
Thales Fragoso
54ad2a41f1
eth-v2: Work around missing AF for REF_CLK
2021-06-16 16:48:35 +02:00
Thales Fragoso
0c837f07c0
eth-v2: Enable clocks in new
2021-06-16 16:48:35 +02:00
Thales Fragoso
e039c7c42c
eth-v2: Remove Instance trait
2021-06-16 16:48:35 +02:00
Thales Fragoso
05a239faf6
eth-v2: Implement embassy-net's Device Trait and fix Drop
2021-06-16 16:48:35 +02:00
Thales Fragoso
4cffa200bd
eth: Add lan8742a PHY
2021-06-16 16:48:35 +02:00
Thales Fragoso
46e1bae9e3
eth-v2: Start Ethernet peripheral implementation
2021-06-16 16:48:35 +02:00
Ulf Lilleengen
56c5218292
Prescaler 1 means divide by 3 on WL55
2021-06-16 16:21:16 +02:00
Ulf Lilleengen
383beb37b3
Rename from wl55 to wl5x and enable debug wfe
2021-06-16 16:07:21 +02:00
Ulf Lilleengen
b6a8703698
Add support for generating PAC for dual cores
...
* Chips that have multiple cores will be exposed as chipname_corename,
i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
and pick the first and only core from the list
* Add support for stm32wl55 chip family
2021-06-16 15:12:07 +02:00
Ulf Lilleengen
8ae4f47d3d
Fix compile
2021-06-15 16:44:00 +02:00
Ulf Lilleengen
49fad2de8a
Use correct frequencies for timers
2021-06-15 16:07:23 +02:00
Ulf Lilleengen
4b406dd107
Remove default rcc impl
2021-06-14 20:24:51 +02:00
Bob McWhirter
d58fb11b2e
ADCv3 and example.
2021-06-14 13:20:42 -04:00
Ulf Lilleengen
531093f281
Derive SPI v1 and v3 clocks automatically
2021-06-14 11:58:16 +02:00
Ulf Lilleengen
5e1b0a5398
Add wb55 clocks
2021-06-14 11:41:02 +02:00
Ulf Lilleengen
ee9f67fa01
Add common types
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a2da2a6db2
Remove unused l0 code
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
95532726b2
Add minimal RCC impls for L4 and F4
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a13e07625f
Add ... c1?
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
0b52731897
Add clocks for h7
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
2c63393c9e
Add Clock type per RCC family
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
952f525af5
Provide a way for a peripheral to query its clock frequency
...
Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
2021-06-14 11:33:11 +02:00
Dominik Boehi
9edb6e41ce
Make gen.py work without CSafeLoader
2021-06-12 18:28:21 +02:00
Dominik Boehi
0eab96f573
Initial support and example for STM32WB55
2021-06-12 07:06:36 +02:00
Ulf Lilleengen
0a9022d59f
Enable timer clock in RCC on timer start
...
* Moves the tim2-specific code into macro which always uses TIM2
* For peripherals without clock specified, attempt to locate enable and
reset registers in the RCC block matching the peripheral name. This
could be useful for peripherals where deducing the clock name might
not be feasible, but it remains to be tested with more chip families
to see if it is sufficiently accurate.
2021-06-10 09:37:30 +02:00
Ulf Lilleengen
1bb7123156
Add examples for STM32L0
2021-06-09 23:09:48 +02:00
Ulf Lilleengen
f3d1ac6623
Enable clock for RNG
2021-06-09 13:54:53 +02:00
Ulf Lilleengen
939ea3bbd0
Reduce generics noise
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ed29d82071
Use critical_section
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
212bda0940
Enable clock for SPI v1 and v3
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
a57482fddd
Cargo fmt
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ee3b82b743
Auto generate SPI v2 clock enable
...
Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral.
Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
a63388874a
Update after name fix
2021-06-07 14:06:54 +02:00
Ulf Lilleengen
f24c38f2a4
Fix
2021-06-07 13:51:06 +02:00
Ulf Lilleengen
1cd2c55b7c
Fix stm32l0 build
2021-06-07 12:19:09 +02:00
Ulf Lilleengen
f5e2fb9a5a
Update to new api
2021-06-07 12:03:31 +02:00
Dario Nieuwenhuis
0ffa78aca1
Use macrotables from build.rs
2021-06-07 05:12:10 +02:00
Dario Nieuwenhuis
3be49d3e79
fmt: Add dunmy use to avoid "unused variable" errors when no log is enabled.
2021-06-07 03:21:37 +02:00
Dario Nieuwenhuis
ef1ebefec0
fmt: use absolute paths
2021-06-07 03:15:05 +02:00
Dario Nieuwenhuis
e7dc5c0939
fmt: make all macros macro_rules so scoping is consistent.
2021-06-07 00:16:39 +02:00
Rukai
010b2b9497
Fix stm32 warnings
2021-06-06 00:46:20 +10:00
Bob McWhirter
b4dca64e20
Move most of DMA out of gen.py.
2021-06-03 14:53:48 -04:00
Bob McWhirter
240616aa72
General clean-up and removal of dead code.
2021-06-03 14:25:17 -04:00
Bob McWhirter
d75bf143eb
Remove the exti_interrupts table.
2021-06-03 14:18:58 -04:00
Bob McWhirter
2c722ec0ee
Migrate sdmmc to macro tables.
2021-06-03 13:50:48 -04:00
Bob McWhirter
fe47f781be
Migrate exti_irq stuff to macro tables.
2021-06-03 13:35:27 -04:00
Bob McWhirter
75dc0fd542
Migrate TIM[2-5] to macro tables.
2021-06-03 13:23:21 -04:00
Bob McWhirter
c00a85f9a9
Refactor SPI signal pin macro.
2021-06-03 13:12:38 -04:00
