e1cccc8391
Move Spi to mod (without NoDma defaults)
2021-12-06 14:47:50 -06:00
aeb69a7665
Track current word size in v2 and v3 also
2021-12-06 14:24:02 -06:00
d51885c0eb
Move WordSize methods to mod
2021-12-06 14:13:25 -06:00
d426caefbf
Move NoPin impls from v1 to mod
2021-12-06 14:02:21 -06:00
81ec4c82fd
Flush MISO before transfer operation
2021-12-03 09:53:28 +01:00
6e0eb33ea8
Downcast timer to GP16 for time drivers.
2021-12-02 18:07:05 +01:00
f0cb77443c
Fix wrong pin configuration in STM32's SPI v3.
2021-12-01 22:18:14 +01:00
b0fabfab5d
Update stm32-data: rcc regs info comes from yamls now.
2021-11-29 02:28:02 +01:00
25b49a8a2a
Remove common clock types
...
Different STM32 RCC peripherals have different capabilities and register
values. Define types for each RCC types inside each module to ensure
full range of capabilities for each family can be used
2021-11-28 16:46:08 +01:00
006e567716
stm32/pwm: allow using the advanced timer instances too.
2021-11-27 03:06:53 +01:00
d7d1258411
stm32/pwm: small cleanups
2021-11-27 03:05:10 +01:00
22fad1e7bc
stm32/pwm: impl instance/pin for all chips
2021-11-27 03:04:50 +01:00
8211d58ee2
stm32/pwm: initial commit
2021-11-27 02:50:30 +01:00
88d4b0c00d
stm32: add stm32g4 support.
2021-11-27 02:34:23 +01:00
cd9a1d547c
Ensure SPI DMA write is completed
...
Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.
2021-11-24 14:59:18 +01:00
e187f50f4b
stm32: remove unused deps
2021-11-24 01:41:51 +01:00
dfb6d407a1
stm32: rename core features from _cmX to -cmX, cleanup gen.
2021-11-23 23:49:06 +01:00
eac604accd
Fix missing lifetime bounds
2021-11-21 10:10:28 +00:00
24e5013c00
Allow unused to fix build failure in u5
2021-11-17 21:43:05 +01:00
ee1490bce1
Move to the newly released bxcan crate that supports defmt 0.3.
2021-11-15 13:18:53 -05:00
c2da498263
Update to defmt 3.0ish.
...
Lots of gitrevs deps.
2021-11-15 11:09:08 -05:00
8193885cb5
Merge #482
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482: Add MCO peripheral. r=Dirbaio a=matoushybl
This PR adds an abstraction over STM32 RCC feature called MCO (Microcontroller Clock Output). The clock output can bind to several clock sources and then can be scaled using a prescaler.
Given that from the embassy ecosystem the RCC is generaly invisible to the user, the MCO was implemented as a separate peripheral bound to the pin where the clock should appear.
Co-authored-by: Matous Hybl <hyblmatous@gmail.com >
2021-11-11 16:20:02 +00:00
c14642cffc
Add MCO peripheral.
2021-11-11 11:34:09 +01:00
96e2f0dfc5
Merge #468
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468: Add v1c ethernet driver for the STM32F7 family. r=Dirbaio a=matoushybl
Co-authored-by: Matous Hybl <hyblmatous@gmail.com >
2021-11-10 22:07:38 +00:00
f0ba79059e
Add v1c ethernet driver for the STM32F7 family.
2021-11-10 10:16:46 +01:00
12a64b867b
More support for U5 PWR (ish), RCC, and FLASH (ish).
2021-11-08 14:27:33 -05:00
5f124ec49f
Update U5 to init RCC.
2021-11-08 14:20:51 -05:00
9b5d9fbfca
Fix v2 ethernet pin definitions. Fix ethernet example for H7 nucleos.
2021-11-04 16:25:30 +01:00
1bf6e646c9
Merge #465
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465: Adjust for STM32U5. r=lulf a=bobmcwhirter
Co-authored-by: Bob McWhirter <bmcwhirt@redhat.com >
2021-11-02 20:42:41 +00:00
d1272e00bb
Prefix unused variable for now.
2021-11-02 15:45:56 -04:00
44056c2e75
Less allowy.
2021-11-02 15:32:20 -04:00
076c795ebb
Even more allowed unused.
2021-11-02 15:28:14 -04:00
6bbf450478
Allow unused macros temporarily until U5 supports DMA.
2021-11-02 15:20:42 -04:00
205a223af3
Update versions of critical-section and atomic-polyfill
2021-11-02 18:52:03 +01:00
705523d0ea
Fix formatting.
2021-11-02 12:13:42 -04:00
f12b70535b
Adjust for STM32U5.
2021-11-02 12:05:24 -04:00
bbff98ed0d
Move the use inside the macro call, inside another set of braces in case it percolates up twice.
2021-10-26 14:34:03 -04:00
a72816492a
Only attempt to enable the dmamux peri clock if it has an enable bit.
2021-10-26 14:19:03 -04:00
959aecf6ac
Enable the DMAMUX clocks.
2021-10-26 14:01:39 -04:00
015cad84dd
Initial support for STM32F767ZI.
2021-10-26 17:33:28 +02:00
01e5376b25
Merge #456
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456: Fix L4 clock setup for MSI and PLL to allow RNG operation r=Dirbaio a=lulf
Example is tested on STM32L475VG.
Co-authored-by: Ulf Lilleengen <lulf@redhat.com >
2021-10-26 11:59:14 +00:00
e55726964d
Fix clock setup for MSI and PLL to allow RNG opereation
...
Add RNG example using PLL as clock source.
2021-10-26 13:45:53 +02:00
f8ebc967a9
Add implementation of async trait for STM32 I2C v2
...
* Add DMA read implementation for I2C v2
* Add example using DMA for I2C
2021-10-21 12:30:02 +02:00
d2a79a46c5
Configure the correct pin instances
2021-10-21 11:57:00 +02:00
43a7226d8b
inline FRE register check for SPI on F1
2021-10-11 23:33:32 +02:00
2cbb8a7ece
Add AFType::Input for input configurations.
2021-10-11 22:57:21 +02:00
259e84e68e
Make miso/mosi optional when for unidirectional spi
...
Only suported on v1 currently
2021-10-11 22:57:21 +02:00
c44bed300b
Correctly set alternate function for stm32f1 gpios
2021-10-11 22:57:21 +02:00
091e7e1f98
Generate USART pin definitions for stm32f1
2021-10-11 22:57:21 +02:00
39880de958
partial alternate function configuration on STM32f1
2021-10-11 22:57:10 +02:00
