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324 Commits

Author SHA1 Message Date
Vincent Stakenburg
7d6d274d55 Add MSI and PLL clock source for L4 2021-09-24 18:27:39 +02:00
Ulf Lilleengen
b6fc19182b Add pwr for L1 and update RCC to new reg block 2021-09-23 14:51:16 +02:00
Ulf Lilleengen
c79485c286 Support for STM32L1 
* Add RCC
* Fix more issues with dash in chip names
* Update stm32-data version
* Add blinky and spi example
 2021-09-21 14:50:23 +02:00
Ulf Lilleengen
fb697a2657 Updates 2021-09-15 12:46:20 +02:00
Ulf Lilleengen
7ad6280e65 Add HAL for SubGhz peripheral for STM32 WL series 
Based on the HAL from stm32wl, the peripheral driver has been
modified to fit into embassy, using the embassy APIs, providing
operation of the radio peripheral.

The initial version does not offer any async APIs, but the example
shows how the radio IRQ can be used to perform async TX of the radio.
 2021-09-02 10:39:56 +02:00
Ben Gamari
e2f71ffbbd Add support for STM32G0 2021-08-20 00:15:11 +02:00
Dario Nieuwenhuis
174c51f097 stm32/metapac: check GPIO RCC regs are always found. 2021-08-19 23:59:50 +02:00
Dario Nieuwenhuis
2c992f7010 stm32: move dbgmcu stuff to toplevel config setting, defaulting to true. 2021-08-19 23:50:19 +02:00
Dario Nieuwenhuis
9f51f9a170 stm32/wl: add stub APB3 to get it to build. 
Completely untested.
 2021-08-19 22:51:41 +02:00
Dario Nieuwenhuis
637fcdd316 stm32/rcc: update for new version naming 2021-08-19 22:17:45 +02:00
Ulf Lilleengen
61409e2fb6 Add example for STM32WL55 2021-08-17 16:22:47 +02:00
Ben Gamari
41aaff95f8 stm32h7: Use unwrap! 2021-08-05 22:39:59 +02:00
Ben Gamari
e44acd0d56 stm32f4: Use unwrap! where possible 2021-08-05 22:39:59 +02:00
Bob McWhirter
f4971fbb79 Further work sharing config for example and removing duplicated code. 2021-08-04 13:39:02 -04:00
Bob McWhirter
03f15d3a60 Remove builders from Config(s) and examples. 2021-08-04 11:32:39 -04:00
Bob McWhirter
88c11a653c Formatting fixes. 2021-08-03 14:12:11 -04:00
Bob McWhirter
d7409d63e8 Enhance Rcc configuration to be more fluentish. 
Clean up H7 examples to remove all vegan HALs and PACs.
 2021-08-03 13:57:18 -04:00
Dario Nieuwenhuis
3835278567
Merge pull request #321 from thalesfragoso/f4-pll 
F4 PLL
 2021-07-31 11:08:46 +02:00
Thales Fragoso
21e3acaa00 stm32: Use build.rs to generate a more coarse feature 2021-07-31 02:52:26 -03:00
Thales Fragoso
0421c57bd6 F4: Add PWR configuration to PLL 2021-07-29 18:43:15 -03:00
Thales Fragoso
5cfb9adad8 f4-pll: Add max values per chip 2021-07-29 18:43:15 -03:00
Thales Fragoso
e7714983b3 f4-rcc: Add option to enable debug_wfe and add hello example 2021-07-29 18:43:15 -03:00
Thales Fragoso
5abaf8e9d6 Start working on the F4 PLL 2021-07-29 18:43:13 -03:00
Timo Kröger
9342497132 stm32wl55: Use Dbgmcu::enable_all 2021-07-29 17:38:40 +02:00
Timo Kröger
cad43587e6 stm32l0: Use embassy::main for examples 2021-07-29 17:37:32 +02:00
Timo Kröger
2a4890165d stm32f0: Enable debug access in low power modes 2021-07-29 15:35:23 +02:00
Dario Nieuwenhuis
7bfb763e09 Rename embassy-extras to embassy-hal-common 2021-07-29 13:44:51 +02:00
Thales Fragoso
2f08c7ced5 stm32: Allow for RccPeripheral without reset field 
This fix build on F0, since it doesn't have DMARST. This change makes
RccPeripheral::reset a no-op on peripherals where a reset field couldn't
be found
 2021-07-15 13:25:51 -03:00
Bob McWhirter
06e899b14c Adjust to DMA1EN in the rcc for l0. 2021-07-13 10:09:35 -04:00
Bob McWhirter
13975a0818 Try to improve H7 clockstuff. 2021-07-13 10:09:35 -04:00
Thales Fragoso
c2f595b26a F0: Fix missing apb2 clock 2021-07-03 02:12:22 -03:00
Bob McWhirter
c53ab325c1 Wire up DMA with USART v1. 2021-06-29 11:01:57 -04:00
Thales Fragoso
409884be2a Add F0 RCC 2021-06-24 19:21:56 -03:00
Dario Nieuwenhuis
5a4e3ceb88 Update stm32-data (adds DBGMCU to all chips) 2021-06-21 01:38:59 +02:00
Ulf Lilleengen
56c5218292 Prescaler 1 means divide by 3 on WL55 2021-06-16 16:21:16 +02:00
Ulf Lilleengen
383beb37b3 Rename from wl55 to wl5x and enable debug wfe 2021-06-16 16:07:21 +02:00
Ulf Lilleengen
b6a8703698 Add support for generating PAC for dual cores 
* Chips that have multiple cores will be exposed as chipname_corename,
  i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
  and pick the first and only core from the list
* Add support for stm32wl55 chip family
 2021-06-16 15:12:07 +02:00
Ulf Lilleengen
8ae4f47d3d Fix compile 2021-06-15 16:44:00 +02:00
Ulf Lilleengen
49fad2de8a Use correct frequencies for timers 2021-06-15 16:07:23 +02:00
Ulf Lilleengen
4b406dd107 Remove default rcc impl 2021-06-14 20:24:51 +02:00
Ulf Lilleengen
5e1b0a5398 Add wb55 clocks 2021-06-14 11:41:02 +02:00
Ulf Lilleengen
ee9f67fa01 Add common types 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a2da2a6db2 Remove unused l0 code 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
95532726b2 Add minimal RCC impls for L4 and F4 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a13e07625f Add ... c1? 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
0b52731897 Add clocks for h7 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
2c63393c9e Add Clock type per RCC family 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
952f525af5 Provide a way for a peripheral to query its clock frequency 
Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
1bb7123156 Add examples for STM32L0 2021-06-09 23:09:48 +02:00
Ulf Lilleengen
ed29d82071 Use critical_section 2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ee3b82b743 Auto generate SPI v2 clock enable 
Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral.

Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.
 2021-06-08 17:20:29 +02:00
Ulf Lilleengen
a63388874a Update after name fix 2021-06-07 14:06:54 +02:00
Ulf Lilleengen
1cd2c55b7c Fix stm32l0 build 2021-06-07 12:19:09 +02:00
Ulf Lilleengen
f5e2fb9a5a Update to new api 2021-06-07 12:03:31 +02:00
Dario Nieuwenhuis
e7dc5c0939 fmt: make all macros macro_rules so scoping is consistent. 2021-06-07 00:16:39 +02:00
Ulf Lilleengen
c3a521066d Add utility to enable debug 2021-06-02 15:23:10 +02:00
Ulf Lilleengen
4863d5e01e Add a way to enable more features of the STM32L0 RCC 
Add ability to enable the hsi48 clock. Code modified from the STM32L0XX
hal
 2021-06-02 14:28:33 +02:00
Dario Nieuwenhuis
d24b67512f More fixes 2021-05-31 03:21:44 +02:00
Dario Nieuwenhuis
d8e4421fc6 Add stm32-metapac crate, with codegen in rust 2021-05-31 02:40:58 +02:00
Ulf Lilleengen
3669eba561 Use builder 2021-05-27 10:01:40 +02:00
Ulf Lilleengen
a41a812345 Move clocks to rcc mod 2021-05-27 09:50:11 +02:00
Ulf Lilleengen
6eaf224fec No more systemclock 2021-05-26 21:46:57 +02:00
Ulf Lilleengen
bfa999a2e0 Assume tim2 in macro and remove clock setup in chip specific rcc init 
Add temporary start_tim2() fn to Clock to assist macro in starting
embassy clock
 2021-05-26 21:42:07 +02:00
Ulf Lilleengen
f960f5b105 Rework 2021-05-26 13:55:25 +02:00
Ulf Lilleengen
9743c59ad4 Simplify 2021-05-26 13:29:11 +02:00
Ulf Lilleengen
ea67940743 Refactor 2021-05-26 13:08:14 +02:00
Ulf Lilleengen
c501b162fc Enable clock by default for stm32l0 
Modify init function to return a Clock instance defined by a per-chip
SystemClock type and use this in macro setup

A proof of concept implementation for STM32 L0 chips.

This allows using embassy::main macros for STM32 devices that have the
clock setup logic.
 2021-05-26 12:33:07 +02:00
Ulf Lilleengen
ef254647f7 Add stm32l0 2021-05-25 13:32:10 +02:00
Ulf Lilleengen
1c10e746b6 Re-adds embassy macros for stm32 
* Hook RCC config into chip config and use chip-specific RCC init
  function
* RTC/clock setup is ignored for now
 2021-05-25 13:30:42 +02:00
Thales Fragoso
2605dabca3 H7 RCC: Fix off by one error 2021-05-21 20:20:17 -03:00
Thales Fragoso
1689ab2f8b H7 RCC: Setup DBGMCU to enable debugging during wfi/wfe 2021-05-21 20:20:17 -03:00
Thales Fragoso
7f65f491e5 Finish initial H7 RCC support 2021-05-21 20:16:25 -03:00
Thales Fragoso
2ea12d96ee More work on H7 RCC 2021-05-21 20:13:39 -03:00
Thales Fragoso
054f0d51dc H7: Add initial PLL configuration 2021-05-21 20:13:37 -03:00