VasanthakumarV
3f33d307ff
[feature] Add rcc register support for F3
2021-12-13 14:50:13 +05:30
VasanthakumarV
e2c074d133
[feature] Add pwr register support for F3
2021-12-13 13:49:41 +05:30
huntc
45ef944457
Stm flush required implementing also, along with std alloc split
2021-12-10 15:11:41 +11:00
Matous Hybl
1dd5a71c07
Add DCMI peripheral support.
2021-12-09 12:56:39 +01:00
Dario Nieuwenhuis
4ddd23d623
stm32/usart: unify v1 and v2
2021-12-08 05:12:48 +01:00
Dario Nieuwenhuis
022c4cb739
stm32/dma: simplify impls a bit.
2021-12-08 03:30:07 +01:00
Dario Nieuwenhuis
b316d2620c
stm32/dma: improve trait docs, seal Word.
2021-12-08 03:18:15 +01:00
Dario Nieuwenhuis
6179da6b9c
stm32/dma: eagerly start transfers when calling the functions.
...
`async fn`s do nothing until polled, but we want the DMA transfer to
immediately start in this case. Drivers rely on it. Some require special
orders, such as "start DMA, start SPI, then wait for DMA" which is awkward
to do without eager start.
Also use a manually-impl'd future, this allows getting rid of the "double"
Unborrow channel clone.
2021-12-08 03:04:39 +01:00
Dario Nieuwenhuis
4e349d0f5d
stm32/dma: use the right waker slot number for DMA2 (must add 8)
2021-12-08 01:54:31 +01:00
Dario Nieuwenhuis
fd2fe62b5f
stm32/dma: rename is_stopped to is_running.
...
Note that this does NOT invert the result of `en()` because it was
wrong before.
2021-12-08 01:51:39 +01:00
Matous Hybl
b2910558d3
Refactor DMA traits.
2021-12-07 21:43:47 +01:00
Joshua Salzedo
e2719aba10
Further extend the dma channel trait
2021-12-07 21:43:47 +01:00
Joshua Salzedo
93e047ede2
cargo fmt
2021-12-07 21:43:47 +01:00
Joshua Salzedo
3411039cb9
Implement extended Channel trait to bdma.rs
2021-12-07 21:43:47 +01:00
Joshua Salzedo
2d2c6d0e01
Implement extended Channel trait to dma.rs
2021-12-07 21:43:47 +01:00
Joshua Salzedo
3272987d92
Expand channel trait
2021-12-07 21:43:47 +01:00
Ulf Lilleengen
f9ac0c8047
Add back MISO flush
2021-12-07 09:40:45 +01:00
Grant Miller
79baa04118
Implement blocking traits with a macro
2021-12-07 00:03:52 -06:00
Grant Miller
bf1f80afa1
Unify blocking trait impls
2021-12-07 00:03:52 -06:00
Grant Miller
3a17e3a2a5
Move async trait impls to mod
2021-12-07 00:03:52 -06:00
Grant Miller
20d2151b1d
check_error_flags function
2021-12-07 00:03:52 -06:00
Grant Miller
496579b48b
Move Word trait to mod
2021-12-07 00:03:52 -06:00
Grant Miller
7c78247be3
v2: set frxth and ds in new
2021-12-06 22:36:53 -06:00
Grant Miller
d76bc45e30
Move Spi drop impl to mod
2021-12-06 17:19:55 -06:00
Grant Miller
bd9e730024
Move set_word_size to mod
2021-12-06 16:47:08 -06:00
Grant Miller
a35b7d90bc
Add tx_ptr and rx_ptr methods
2021-12-06 16:33:06 -06:00
Grant Miller
a35f337bd6
Move Spi::new and Spi::compute_baud_rate to mod
2021-12-06 15:19:24 -06:00
Grant Miller
75374ce7e8
Fix ssoe in v1
2021-12-06 14:57:53 -06:00
Grant Miller
e1cccc8391
Move Spi to mod (without NoDma defaults)
2021-12-06 14:47:50 -06:00
Grant Miller
aeb69a7665
Track current word size in v2 and v3 also
2021-12-06 14:24:02 -06:00
Grant Miller
d51885c0eb
Move WordSize methods to mod
2021-12-06 14:13:25 -06:00
Grant Miller
d426caefbf
Move NoPin impls from v1 to mod
2021-12-06 14:02:21 -06:00
Ulf Lilleengen
81ec4c82fd
Flush MISO before transfer operation
2021-12-03 09:53:28 +01:00
Matous Hybl
6e0eb33ea8
Downcast timer to GP16 for time drivers.
2021-12-02 18:07:05 +01:00
Matous Hybl
f0cb77443c
Fix wrong pin configuration in STM32's SPI v3.
2021-12-01 22:18:14 +01:00
Dario Nieuwenhuis
b0fabfab5d
Update stm32-data: rcc regs info comes from yamls now.
2021-11-29 02:28:02 +01:00
Ulf Lilleengen
25b49a8a2a
Remove common clock types
...
Different STM32 RCC peripherals have different capabilities and register
values. Define types for each RCC types inside each module to ensure
full range of capabilities for each family can be used
2021-11-28 16:46:08 +01:00
Dario Nieuwenhuis
006e567716
stm32/pwm: allow using the advanced timer instances too.
2021-11-27 03:06:53 +01:00
Dario Nieuwenhuis
d7d1258411
stm32/pwm: small cleanups
2021-11-27 03:05:10 +01:00
Dario Nieuwenhuis
22fad1e7bc
stm32/pwm: impl instance/pin for all chips
2021-11-27 03:04:50 +01:00
Ben Gamari
8211d58ee2
stm32/pwm: initial commit
2021-11-27 02:50:30 +01:00
Dario Nieuwenhuis
88d4b0c00d
stm32: add stm32g4 support.
2021-11-27 02:34:23 +01:00
Ulf Lilleengen
cd9a1d547c
Ensure SPI DMA write is completed
...
Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.
2021-11-24 14:59:18 +01:00
Wilfried Chauveau
eac604accd
Fix missing lifetime bounds
2021-11-21 10:10:28 +00:00
Dario Nieuwenhuis
24e5013c00
Allow unused to fix build failure in u5
2021-11-17 21:43:05 +01:00
Bob McWhirter
c2da498263
Update to defmt 3.0ish.
...
Lots of gitrevs deps.
2021-11-15 11:09:08 -05:00
bors[bot]
8193885cb5
Merge #482
...
482: Add MCO peripheral. r=Dirbaio a=matoushybl
This PR adds an abstraction over STM32 RCC feature called MCO (Microcontroller Clock Output). The clock output can bind to several clock sources and then can be scaled using a prescaler.
Given that from the embassy ecosystem the RCC is generaly invisible to the user, the MCO was implemented as a separate peripheral bound to the pin where the clock should appear.
Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-11-11 16:20:02 +00:00
Matous Hybl
c14642cffc
Add MCO peripheral.
2021-11-11 11:34:09 +01:00
bors[bot]
96e2f0dfc5
Merge #468
...
468: Add v1c ethernet driver for the STM32F7 family. r=Dirbaio a=matoushybl
Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-11-10 22:07:38 +00:00
Matous Hybl
f0ba79059e
Add v1c ethernet driver for the STM32F7 family.
2021-11-10 10:16:46 +01:00
Bob McWhirter
12a64b867b
More support for U5 PWR (ish), RCC, and FLASH (ish).
2021-11-08 14:27:33 -05:00
Bob McWhirter
5f124ec49f
Update U5 to init RCC.
2021-11-08 14:20:51 -05:00
Matous Hybl
9b5d9fbfca
Fix v2 ethernet pin definitions. Fix ethernet example for H7 nucleos.
2021-11-04 16:25:30 +01:00
Bob McWhirter
d1272e00bb
Prefix unused variable for now.
2021-11-02 15:45:56 -04:00
Bob McWhirter
44056c2e75
Less allowy.
2021-11-02 15:32:20 -04:00
Bob McWhirter
076c795ebb
Even more allowed unused.
2021-11-02 15:28:14 -04:00
Bob McWhirter
6bbf450478
Allow unused macros temporarily until U5 supports DMA.
2021-11-02 15:20:42 -04:00
Bob McWhirter
705523d0ea
Fix formatting.
2021-11-02 12:13:42 -04:00
Bob McWhirter
f12b70535b
Adjust for STM32U5.
2021-11-02 12:05:24 -04:00
Bob McWhirter
bbff98ed0d
Move the use inside the macro call, inside another set of braces in case it percolates up twice.
2021-10-26 14:34:03 -04:00
Bob McWhirter
a72816492a
Only attempt to enable the dmamux peri clock if it has an enable bit.
2021-10-26 14:19:03 -04:00
Bob McWhirter
959aecf6ac
Enable the DMAMUX clocks.
2021-10-26 14:01:39 -04:00
Matous Hybl
015cad84dd
Initial support for STM32F767ZI.
2021-10-26 17:33:28 +02:00
bors[bot]
01e5376b25
Merge #456
...
456: Fix L4 clock setup for MSI and PLL to allow RNG operation r=Dirbaio a=lulf
Example is tested on STM32L475VG.
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2021-10-26 11:59:14 +00:00
Ulf Lilleengen
e55726964d
Fix clock setup for MSI and PLL to allow RNG opereation
...
Add RNG example using PLL as clock source.
2021-10-26 13:45:53 +02:00
Ulf Lilleengen
f8ebc967a9
Add implementation of async trait for STM32 I2C v2
...
* Add DMA read implementation for I2C v2
* Add example using DMA for I2C
2021-10-21 12:30:02 +02:00
Ulf Lilleengen
d2a79a46c5
Configure the correct pin instances
2021-10-21 11:57:00 +02:00
Tobias Pisani
43a7226d8b
inline FRE register check for SPI on F1
2021-10-11 23:33:32 +02:00
Tobias Pisani
2cbb8a7ece
Add AFType::Input for input configurations.
2021-10-11 22:57:21 +02:00
Tobias Pisani
259e84e68e
Make miso/mosi optional when for unidirectional spi
...
Only suported on v1 currently
2021-10-11 22:57:21 +02:00
Tobias Pisani
c44bed300b
Correctly set alternate function for stm32f1 gpios
2021-10-11 22:57:21 +02:00
Tobias Pisani
091e7e1f98
Generate USART pin definitions for stm32f1
2021-10-11 22:57:21 +02:00
Tobias Pisani
39880de958
partial alternate function configuration on STM32f1
2021-10-11 22:57:10 +02:00
Tobias Pisani
f9a576d13d
feat: Add spi support for STM32F1 variants
2021-10-11 22:39:48 +02:00
Ben Gamari
006bbea51a
stm32/adc: Add IN0 channel
2021-09-29 00:32:40 -04:00
Ben Gamari
5a38cc2140
stm32/dac: Ensure that clock is enabled
2021-09-29 00:32:40 -04:00
Ben Gamari
0b9961584b
stm32/adc: Ensure that clock is enabled
...
Sadly due to the inconsistency in clocking configuration across devices
we cannot use RccPeripheral.
2021-09-29 00:32:40 -04:00
Ben Gamari
573e6ec373
stm32g0: Add support for low-power run
2021-09-28 21:19:10 -04:00
Ben Gamari
794798e225
stm32g0: Add support for HSI divider
2021-09-28 21:19:10 -04:00
Ben Gamari
aa4069fe10
stm32/adc: Fix ADC support for STM32G0
2021-09-28 21:19:10 -04:00
Ben Gamari
e2e0464d04
stm32/adc: Factor out conversion logic
...
Also guard errata workaround correctly.
2021-09-28 18:00:05 -04:00
Mariusz Ryndzionek
ce361abb1b
Changing the casts (code review request)
2021-09-28 18:31:04 +02:00
Mariusz Ryndzionek
bce909ec1e
Initial STM32F1 family support with two examples for STM32F103C8 (Blue Pill)
2021-09-28 18:31:04 +02:00
Joshua Salzedo
ab60cfd64b
Patch additional regressions
2021-09-27 15:48:56 -07:00
Joshua Salzedo
67e2f9159c
set moder::ALTERNATE last when configuring pins to AF modes.
...
- as per STM32F4xx_hal's impl
2021-09-27 15:27:43 -07:00
Joshua Salzedo
07e20a7443
Pub use version-specific CRC symbols, not just the CRC struct.
2021-09-27 11:17:31 -07:00
Joshua Salzedo
a26ffeb84b
Cargo fmt
2021-09-27 10:49:32 -07:00
Joshua Salzedo
e36d4f460a
Fix variable names in crc_v2/v3.
...
removed `reclaim` in crc_v1.
used write instead of modify.
renamed `init` to `reset` in crc_v1.
2021-09-27 10:46:09 -07:00
Joshua Salzedo
43ad28b9f9
Use unborrow for CRC constructor
...
sort feature gates
fix repetition in CRC config names
2021-09-27 10:38:55 -07:00
Joshua Salzedo
7392e33ad5
cargo fmt
2021-09-26 19:20:21 -07:00
Joshua Salzedo
e67af514e9
Fix v2/3 module paths
2021-09-26 19:15:54 -07:00
Joshua Salzedo
642b0825a6
V3 is just an extension of V2, merge modules.
2021-09-26 19:14:08 -07:00
Joshua Salzedo
f9ff5336d4
Merge all of the crc_v2 configurations into a single modify call
2021-09-26 18:46:19 -07:00
Joshua Salzedo
8fac444c4e
Flesh out v2 config writes
2021-09-26 18:39:55 -07:00
Joshua Salzedo
afef19d813
Start work towards CRC_V2
2021-09-26 18:26:20 -07:00
Joshua Salzedo
7899d73359
Expose read so the value can be obtained without a write.
2021-09-26 17:28:58 -07:00
Joshua Salzedo
c892289b2c
Actually export CRC
2021-09-26 17:26:33 -07:00
Joshua Salzedo
24dea91f5a
Fix interface changes
2021-09-26 17:24:48 -07:00
Joshua Salzedo
e18a27eea2
First pass at CRC_V1
2021-09-26 16:46:17 -07:00
Joshua Salzedo
e527892d89
Start work on CRC_v1
2021-09-26 16:29:22 -07:00
