Ulf Lilleengen
49fad2de8a
Use correct frequencies for timers
2021-06-15 16:07:23 +02:00
Ulf Lilleengen
4b406dd107
Remove default rcc impl
2021-06-14 20:24:51 +02:00
Bob McWhirter
d58fb11b2e
ADCv3 and example.
2021-06-14 13:20:42 -04:00
Ulf Lilleengen
531093f281
Derive SPI v1 and v3 clocks automatically
2021-06-14 11:58:16 +02:00
Ulf Lilleengen
5e1b0a5398
Add wb55 clocks
2021-06-14 11:41:02 +02:00
Ulf Lilleengen
ee9f67fa01
Add common types
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a2da2a6db2
Remove unused l0 code
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
95532726b2
Add minimal RCC impls for L4 and F4
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a13e07625f
Add ... c1?
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
0b52731897
Add clocks for h7
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
2c63393c9e
Add Clock type per RCC family
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
952f525af5
Provide a way for a peripheral to query its clock frequency
...
Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
2021-06-14 11:33:11 +02:00
Dominik Boehi
9edb6e41ce
Make gen.py work without CSafeLoader
2021-06-12 18:28:21 +02:00
Dominik Boehi
0eab96f573
Initial support and example for STM32WB55
2021-06-12 07:06:36 +02:00
Ulf Lilleengen
0a9022d59f
Enable timer clock in RCC on timer start
...
* Moves the tim2-specific code into macro which always uses TIM2
* For peripherals without clock specified, attempt to locate enable and
reset registers in the RCC block matching the peripheral name. This
could be useful for peripherals where deducing the clock name might
not be feasible, but it remains to be tested with more chip families
to see if it is sufficiently accurate.
2021-06-10 09:37:30 +02:00
Ulf Lilleengen
1bb7123156
Add examples for STM32L0
2021-06-09 23:09:48 +02:00
Ulf Lilleengen
f3d1ac6623
Enable clock for RNG
2021-06-09 13:54:53 +02:00
Ulf Lilleengen
939ea3bbd0
Reduce generics noise
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ed29d82071
Use critical_section
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
212bda0940
Enable clock for SPI v1 and v3
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
a57482fddd
Cargo fmt
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ee3b82b743
Auto generate SPI v2 clock enable
...
Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral.
Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
a63388874a
Update after name fix
2021-06-07 14:06:54 +02:00
Ulf Lilleengen
f24c38f2a4
Fix
2021-06-07 13:51:06 +02:00
Ulf Lilleengen
1cd2c55b7c
Fix stm32l0 build
2021-06-07 12:19:09 +02:00
Ulf Lilleengen
f5e2fb9a5a
Update to new api
2021-06-07 12:03:31 +02:00
Dario Nieuwenhuis
0ffa78aca1
Use macrotables from build.rs
2021-06-07 05:12:10 +02:00
Dario Nieuwenhuis
3be49d3e79
fmt: Add dunmy use to avoid "unused variable" errors when no log is enabled.
2021-06-07 03:21:37 +02:00
Dario Nieuwenhuis
ef1ebefec0
fmt: use absolute paths
2021-06-07 03:15:05 +02:00
Dario Nieuwenhuis
e7dc5c0939
fmt: make all macros macro_rules
so scoping is consistent.
2021-06-07 00:16:39 +02:00
Rukai
010b2b9497
Fix stm32 warnings
2021-06-06 00:46:20 +10:00
Bob McWhirter
b4dca64e20
Move most of DMA out of gen.py.
2021-06-03 14:53:48 -04:00
Bob McWhirter
240616aa72
General clean-up and removal of dead code.
2021-06-03 14:25:17 -04:00
Bob McWhirter
d75bf143eb
Remove the exti_interrupts table.
2021-06-03 14:18:58 -04:00
Bob McWhirter
2c722ec0ee
Migrate sdmmc to macro tables.
2021-06-03 13:50:48 -04:00
Bob McWhirter
fe47f781be
Migrate exti_irq stuff to macro tables.
2021-06-03 13:35:27 -04:00
Bob McWhirter
75dc0fd542
Migrate TIM[2-5] to macro tables.
2021-06-03 13:23:21 -04:00
Bob McWhirter
c00a85f9a9
Refactor SPI signal pin macro.
2021-06-03 13:12:38 -04:00
Bob McWhirter
3dd497c1e6
Refactor some I2c signal pin macro.
2021-06-03 13:12:38 -04:00
Bob McWhirter
00892c7362
Migrate USART to macro tables.
2021-06-03 13:12:38 -04:00
Bob McWhirter
6958091b50
Move DAC, I2C, SPI and RNG to macro-tables.
2021-06-03 13:12:38 -04:00
Dario Nieuwenhuis
c7c6b0b464
Merge pull request #211 from bobmcwhirter/dac_v2
...
DAC v2 basics.
2021-06-02 16:16:27 +02:00
Ulf Lilleengen
c3a521066d
Add utility to enable debug
2021-06-02 15:23:10 +02:00
Ulf Lilleengen
4863d5e01e
Add a way to enable more features of the STM32L0 RCC
...
Add ability to enable the hsi48 clock. Code modified from the STM32L0XX
hal
2021-06-02 14:28:33 +02:00
Bob McWhirter
0c54c1afd1
DAC v2 basics.
2021-06-01 12:08:30 -04:00
Ulf Lilleengen
1a9a619033
Implement togglable output pin for Output
2021-05-31 09:33:33 +02:00
Dario Nieuwenhuis
553432a8e8
stm32: remove unused stuff from gen.py
2021-05-31 03:58:03 +02:00
Dario Nieuwenhuis
b2d8d23f4c
more fix
2021-05-31 03:25:10 +02:00
Dario Nieuwenhuis
d24b67512f
More fixes
2021-05-31 03:21:44 +02:00
Dario Nieuwenhuis
c4f8f1655e
Delete unused submodule
2021-05-31 02:59:06 +02:00
Dario Nieuwenhuis
60f12c78dd
Add resolver=2
2021-05-31 02:43:59 +02:00
Dario Nieuwenhuis
d8e4421fc6
Add stm32-metapac crate, with codegen in rust
2021-05-31 02:40:58 +02:00
Ulf Lilleengen
edec5833b3
Refactor SPI and fix write bug
...
* SPI write v2 was hanging in write due to an infinite loop
* SPI word write was not followed by a read back
The u8 and u16 write/read logic have been refactored into write_word and
read_word.
2021-05-27 23:05:42 +02:00
Dario Nieuwenhuis
c4ea7427fa
Update stm32-data
2021-05-27 13:46:46 +02:00
Dario Nieuwenhuis
3f6f1d99bb
Merge pull request #207 from lulf/clock-init
...
Enable clock by default for stm32l0
2021-05-27 13:36:14 +02:00
Ulf Lilleengen
d4dbeb6933
Handle case where pin value could be 0
...
In the case where GPIO mapping could look like this:
PA5:
SPI1_SCK: 0
The pin would not get any generated impl because the if expression would evaluate to false. Fix this for all cases in gen.py by comparing against None
~
2021-05-27 13:25:06 +02:00
Ulf Lilleengen
3669eba561
Use builder
2021-05-27 10:01:40 +02:00
Ulf Lilleengen
a41a812345
Move clocks to rcc mod
2021-05-27 09:50:11 +02:00
Ulf Lilleengen
6eaf224fec
No more systemclock
2021-05-26 21:46:57 +02:00
Ulf Lilleengen
bfa999a2e0
Assume tim2 in macro and remove clock setup in chip specific rcc init
...
Add temporary start_tim2() fn to Clock to assist macro in starting
embassy clock
2021-05-26 21:42:07 +02:00
Ulf Lilleengen
f960f5b105
Rework
2021-05-26 13:55:25 +02:00
Ulf Lilleengen
9743c59ad4
Simplify
2021-05-26 13:29:11 +02:00
Ulf Lilleengen
ea67940743
Refactor
2021-05-26 13:08:14 +02:00
Ulf Lilleengen
c501b162fc
Enable clock by default for stm32l0
...
Modify init function to return a Clock instance defined by a per-chip
SystemClock type and use this in macro setup
A proof of concept implementation for STM32 L0 chips.
This allows using embassy::main macros for STM32 devices that have the
clock setup logic.
2021-05-26 12:33:07 +02:00
Bob McWhirter
a9ec941dca
i2c v1
2021-05-25 14:47:07 -04:00
Bob McWhirter
aed8283cd5
Finalize i2c v2.
2021-05-25 10:02:40 -04:00
Ulf Lilleengen
ef254647f7
Add stm32l0
2021-05-25 13:32:10 +02:00
Ulf Lilleengen
1c10e746b6
Re-adds embassy macros for stm32
...
* Hook RCC config into chip config and use chip-specific RCC init
function
* RTC/clock setup is ignored for now
2021-05-25 13:30:42 +02:00
Thales Fragoso
9c5d4d9f8a
STM32 Clock: Use atomic-polyfill
2021-05-23 17:22:07 -03:00
Thales Fragoso
66f232574a
Update stm32-data and rename RTC to Clock
2021-05-23 17:09:11 -03:00
Thales Fragoso
90b25e70d7
timer-rtc: Already ask for the timer frequency
2021-05-23 16:15:24 -03:00
Thales Fragoso
e501932cb5
Update generated files
2021-05-23 15:59:49 -03:00
Thales Fragoso
13698d58e4
Add timer/rtc impl macro
2021-05-23 15:59:09 -03:00
Thales Fragoso
e49e3723a8
wip timers for embassy rtc
2021-05-22 23:58:40 -03:00
Thales Fragoso
212d905816
Update generated files
2021-05-22 23:55:44 -03:00
Thales Fragoso
2b1d7fe3ee
Use Mutex and CriticalSection from bare-metal 1.0
2021-05-22 23:53:50 -03:00
Thales Fragoso
7c06518c52
Update generated files
2021-05-22 22:27:49 -03:00
Thales Fragoso
706992aef9
Support block names with underscores
2021-05-22 22:25:44 -03:00
Thales Fragoso
5e49a9932f
Update generated files
2021-05-22 22:07:05 -03:00
Thales Fragoso
a0fe9e4645
Add unstable feature to give access to the pac
2021-05-22 15:34:49 -03:00
Thales Fragoso
2605dabca3
H7 RCC: Fix off by one error
2021-05-21 20:20:17 -03:00
Thales Fragoso
f5860c3c4c
Fix import on SDMMC
2021-05-21 20:20:17 -03:00
Thales Fragoso
1689ab2f8b
H7 RCC: Setup DBGMCU to enable debugging during wfi/wfe
2021-05-21 20:20:17 -03:00
Thales Fragoso
f9724fa576
Update generated code
2021-05-21 20:20:12 -03:00
Thales Fragoso
7f65f491e5
Finish initial H7 RCC support
2021-05-21 20:16:25 -03:00
Thales Fragoso
82ca5b495e
Update generated code
2021-05-21 20:14:52 -03:00
Thales Fragoso
2ea12d96ee
More work on H7 RCC
2021-05-21 20:13:39 -03:00
Thales Fragoso
054f0d51dc
H7: Add initial PLL configuration
2021-05-21 20:13:37 -03:00
Thales Fragoso
7e388fcf58
Add pac RCC for H7 (generated)
2021-05-21 20:11:27 -03:00
Dario Nieuwenhuis
447e4e6023
Regen
2021-05-21 19:35:15 +02:00
Dario Nieuwenhuis
35f1f65670
Generate mod regs
just once, so rustfmt is way faster.
2021-05-21 19:34:41 +02:00
Dario Nieuwenhuis
f96db3d9d2
Remove ad-hoc imports from generated code.
2021-05-21 19:29:37 +02:00
Dario Nieuwenhuis
0d08e65235
Regen
2021-05-21 19:05:21 +02:00
Ulf Lilleengen
03bfbe51f5
Create DMA fn to select peripheral based on channel number
2021-05-21 18:38:33 +02:00
Ulf Lilleengen
32fbb32a84
Move exti setup into pac module
2021-05-21 18:38:33 +02:00
Ulf Lilleengen
a95c78b8bd
Merge exti macros into one and use simpler recursion
2021-05-21 18:38:33 +02:00
Ulf Lilleengen
56a902c19f
Update submodule commit
2021-05-21 18:38:33 +02:00
Ulf Lilleengen
b5373a1a64
Allow generating pac for STM32L0
2021-05-21 18:38:33 +02:00
Ulf Lilleengen
9fa5a2920f
Move regs trait implementation into generated pac
...
This allows handling devices that don't have DMA2
2021-05-21 18:38:33 +02:00
Ulf Lilleengen
0cd3236fa3
Generate exti interrupt handlers
...
Match interrupts starting with ^EXTI and generate init code and irq
handler for them
2021-05-21 18:38:33 +02:00