Ulf Lilleengen
f9ac0c8047
Add back MISO flush
2021-12-07 09:40:45 +01:00
Grant Miller
bf1f80afa1
Unify blocking trait impls
2021-12-07 00:03:52 -06:00
Grant Miller
3a17e3a2a5
Move async trait impls to mod
2021-12-07 00:03:52 -06:00
Grant Miller
20d2151b1d
check_error_flags function
2021-12-07 00:03:52 -06:00
Grant Miller
496579b48b
Move Word trait to mod
2021-12-07 00:03:52 -06:00
Grant Miller
d76bc45e30
Move Spi drop impl to mod
2021-12-06 17:19:55 -06:00
Grant Miller
bd9e730024
Move set_word_size to mod
2021-12-06 16:47:08 -06:00
Grant Miller
a35b7d90bc
Add tx_ptr and rx_ptr methods
2021-12-06 16:33:06 -06:00
Grant Miller
a35f337bd6
Move Spi::new and Spi::compute_baud_rate to mod
2021-12-06 15:19:24 -06:00
Grant Miller
e1cccc8391
Move Spi to mod (without NoDma defaults)
2021-12-06 14:47:50 -06:00
Grant Miller
aeb69a7665
Track current word size in v2 and v3 also
2021-12-06 14:24:02 -06:00
Grant Miller
d51885c0eb
Move WordSize methods to mod
2021-12-06 14:13:25 -06:00
Ulf Lilleengen
81ec4c82fd
Flush MISO before transfer operation
2021-12-03 09:53:28 +01:00
Matous Hybl
f0cb77443c
Fix wrong pin configuration in STM32's SPI v3.
2021-12-01 22:18:14 +01:00
Ulf Lilleengen
cd9a1d547c
Ensure SPI DMA write is completed
...
Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.
2021-11-24 14:59:18 +01:00
Ulf Lilleengen
d2a79a46c5
Configure the correct pin instances
2021-10-21 11:57:00 +02:00
Tobias Pisani
259e84e68e
Make miso/mosi optional when for unidirectional spi
...
Only suported on v1 currently
2021-10-11 22:57:21 +02:00
Ulf Lilleengen
7ad6280e65
Add HAL for SubGhz peripheral for STM32 WL series
...
Based on the HAL from stm32wl, the peripheral driver has been
modified to fit into embassy, using the embassy APIs, providing
operation of the radio peripheral.
The initial version does not offer any async APIs, but the example
shows how the radio IRQ can be used to perform async TX of the radio.
2021-09-02 10:39:56 +02:00
Dario Nieuwenhuis
7bfb763e09
Rename embassy-extras to embassy-hal-common
2021-07-29 13:44:51 +02:00
Bob McWhirter
83f63890e5
Actually take a &mut of that read slice.
2021-07-23 13:22:39 -04:00
Bob McWhirter
473a83a937
Adjust how we deal with read/write being different length.
...
Including some docs about it.
Removing the Rx-enablement for write-only operations.
2021-07-23 13:22:39 -04:00
Bob McWhirter
0d2051243e
SPIv2 + DMA.
2021-07-23 13:22:39 -04:00
Ulf Lilleengen
952f525af5
Provide a way for a peripheral to query its clock frequency
...
Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
939ea3bbd0
Reduce generics noise
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ee3b82b743
Auto generate SPI v2 clock enable
...
Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral.
Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.
2021-06-08 17:20:29 +02:00
Rukai
010b2b9497
Fix stm32 warnings
2021-06-06 00:46:20 +10:00
Ulf Lilleengen
edec5833b3
Refactor SPI and fix write bug
...
* SPI write v2 was hanging in write due to an infinite loop
* SPI word write was not followed by a read back
The u8 and u16 write/read logic have been refactored into write_word and
read_word.
2021-05-27 23:05:42 +02:00
Bob McWhirter
b3eda9914b
Use the correct register names.
2021-05-20 14:24:40 -04:00
Bob McWhirter
222faccbab
Formatting.
2021-05-20 14:19:43 -04:00
Bob McWhirter
d890ef98c1
Make SPIv3 work and improve v1 and v2.
2021-05-20 14:13:45 -04:00
Bob McWhirter
0d1a0934c4
Cargo fmt.
2021-05-17 13:58:49 -04:00
Bob McWhirter
1872824d56
Add SPI v3, fix up v2's af_num and remove extraneous Error enums.
2021-05-17 13:56:13 -04:00
Dario Nieuwenhuis
2303364322
Standardize module structure, fix some build failures
2021-05-17 02:04:51 +02:00
