539: nrf: async usb r=Dirbaio a=jacobrosenthal
Frankensteined together from this old pr https://github.com/embassy-rs/embassy/pull/115 and nrf-usdb
~Doesnt currently work..~
Co-authored-by: Jacob Rosenthal <jacobrosenthal@gmail.com>
545: Add adapter for implementing async traits for blocking types r=lulf a=lulf
This allows writing drivers relying on async traits, while still
functioning with implementations that already implement the embedded-hal
traits.
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
563: Initial ADC support for on STM32F1xx r=Dirbaio a=sjoerdsimons
Add an ADC implementation for F1 based chips. Primarily tested using ADC1, proper functionality for ADC2 probably needs some extra work as it's mainly a slave and can't e.g. measure vrefint by itself.
Needs https://github.com/embassy-rs/stm32-data/pull/115
Co-authored-by: Sjoerd Simons <sjoerd@collabora.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
559: USART DMA example for the STM32F7 r=Dirbaio a=olofwalker
This small PR adds the USART DMA write an example for the STM32F7. The example has been tested on a Nucleo-f767zi board.
Output from `DEFMT_LOG=info cargo run --bin usart_dma`
```
Running `probe-run --chip STM32F767ZITx target/thumbv7em-none-eabihf/debug/usart_dma`
(HOST) INFO flashing program (108 pages / 108.00 KiB)
(HOST) INFO success!
────────────────────────────────────────────────────────────────────────────────
0 INFO Hello World!
└─ usart_dma::__cortex_m_rt_main @ src/bin/usart_dma.rs:39
1 INFO wrote DMA
└─ usart_dma::main_task::task::{generator#0} @ src/bin/usart_dma.rs:31
```
Co-authored-by: Robert Walker <rgit@walker.st>
558: Port buffered uart to v1 stm32 hardware r=Dirbaio a=DCNick3
#526 seems to suggest that it will be rewritten for DMA support, but I am not sure how to implement it and the port was quite straightforward, so here it is. It might be immediately useful before DMA version will be implemented
Note that I have not tested this on v2 hardware
Co-authored-by: Nikita Strygin <nikita6@bk.ru>
561: stm32/dac: Fix disable_channel r=Dirbaio a=bgamari
Previously disable_channel enabled rather than disabled the requested
channel due to an apparent copy-paste error. Refactor to eliminate this
sort of issue by construction.
Co-authored-by: Ben Gamari <ben@smart-cactus.org>
Previously disable_channel enabled rather than disabled the requested
channel due to an apparent copy-paste error. Refactor to eliminate this
sort of issue by construction.
555: Use cortex-m only on cortex-m archs. r=Dirbaio a=Dirbaio
Without this, build fails for iOS.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
554: Update stm32-data with F3 Timer register changes r=Dirbaio a=VasanthakumarV
Changes to `stm32-data` as part of https://github.com/embassy-rs/stm32-data/pull/112
Co-authored-by: VasanthakumarV <vasanth260m12@gmail.com>
551: nrf/gpio: add infallible inherent methods, remove some duplication. r=Dirbaio a=Dirbaio
Add infallible inherent methods, so that users don't have to import a trait, or `.unwrap()`.
This implements Input and Output using FlexPin, to avoid some code duplication.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
This allows writing drivers relying on async traits, while still
functioning with implementations that already implement the embedded-hal
traits.
Add examples to stm32l4 for using this feature.
548: Set Uarte log levels to trace r=lulf a=huntc
I noticed lots of logging which really slows things down and is not useful outside of a debugging context, hence set to trace.
Co-authored-by: huntc <huntchr@gmail.com>
544: Introduces split on the nRF Uarte r=Dirbaio a=huntc
A new `split` method is introduced such that the Uarte tx and rx can be used from separate tasks. An MPSC is used in an example to illustrate how data may be passed between these tasks.
The approach taken within the `Uarte` struct is to split into tx and rx fields on calling `Uarte::new`. These fields are returned given a call to `Uarte::split`, but otherwise, if that call isn't made, then the API remains as it was before.
Here's a snippet from a new example introduced:
```rust
#[embassy::main]
async fn main(spawner: Spawner, p: Peripherals) {
// ...
let uart = uarte::Uarte::new(p.UARTE0, irq, p.P0_08, p.P0_06, NoPin, NoPin, config);
let (mut tx, rx) = uart.split();
// ...
// Spawn a task responsible purely for reading
unwrap!(spawner.spawn(reader(rx, s)));
// ...
// Continue reading in this main task and write
// back out the buffer we receive from the read
// task.
loop {
if let Some(buf) = r.recv().await {
info!("writing...");
unwrap!(tx.write(&buf).await);
}
}
}
#[embassy::task]
async fn reader(mut rx: UarteRx<'static, UARTE0>, s: Sender<'static, Noop, [u8; 8], 1>) {
let mut buf = [0; 8];
loop {
info!("reading...");
unwrap!(rx.read(&mut buf).await);
unwrap!(s.send(buf).await);
}
}
```
Co-authored-by: huntc <huntchr@gmail.com>
540: Initial support for STM32F3 r=Dirbaio a=VasanthakumarV
The [companion PR](https://github.com/embassy-rs/stm32-data/pull/109) in `stm32-data` should be merged before this PR.
The examples were tested on an STM32F303VC MCU.
Co-authored-by: VasanthakumarV <vasanth260m12@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
543: Incrementally merge STM32 SPI versions, Part 3 r=Dirbaio a=GrantM11235
Notable changes:
- `SPE` is now disabled before `TXDMAEN` and `RXDMAEN` are disabled. This is the "mandatory" sequence for v2 and v3 (and maybe v1 as well, but I can't find it in the reference manual).
- v1's `write_dma_u8` now waits for idle and disables `TXDMAEN` after the transfer is complete, just like everything else.
Co-authored-by: Grant Miller <GrantM11235@gmail.com>
