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d6faf69e09
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42 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
d6faf69e09
Merge pull request #378 from numero-744/gen-features-using-rust-not-python 
Use our beloved Rust instead of Python
 2021-09-13 16:47:01 +02:00
Côme ALLART
99ccf18160 fix(gen-features): keep data files order 2021-09-11 20:04:57 +02:00
Dario Nieuwenhuis
f2623e7e9b Update lots of deps 2021-09-11 01:35:23 +02:00
Côme ALLART
addee8778d refactor(gen-features): use Rust instead of Python 
Added support for /stm32-metapac
 2021-09-05 20:19:13 +02:00
Dario Nieuwenhuis
d3aeb45fb3 Update cortex-m-rt to v0.7 for stm32, rp. 2021-08-19 00:56:11 +02:00
Bob McWhirter
63b32b39e1 Use an em bikeshed instead of an underscore bikeshed. 2021-08-02 13:29:06 -04:00
Bob McWhirter
5f9447abb4 Put the implicit memory.x behind a memory_x feature on embassy-stm32. 2021-08-02 13:21:30 -04:00
Dario Nieuwenhuis
1d64421fb4 Fix "can't find crate for std" for stm32-metapac-gen deps. 2021-07-13 05:47:10 +02:00
Bob McWhirter
497d3aa153 Add USARTv3 support. 2021-07-01 11:30:54 -04:00
Bob McWhirter
2a25de3d3e Make the metapac gen enr/rst missing regs non-fatal to the build. 
Should be solved in a separate effort.
 2021-06-29 12:55:15 -04:00
Bob McWhirter
24f18819c8 Adjust example for RCC and DMA. 2021-06-29 11:01:57 -04:00
Bob McWhirter
b88fc2847a Checkpoint with lifetime issues. 2021-06-29 11:01:57 -04:00
Bob McWhirter
1732551db4 Generate dma-related macro tables. 2021-06-29 11:01:45 -04:00
Thales Fragoso
210104e6dc Remove unused gpio_af from codegen 2021-06-24 19:23:51 -03:00
Dario Nieuwenhuis
5a4e3ceb88 Update stm32-data (adds DBGMCU to all chips) 2021-06-21 01:38:59 +02:00
Ulf Lilleengen
b6a8703698 Add support for generating PAC for dual cores 
* Chips that have multiple cores will be exposed as chipname_corename,
  i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
  and pick the first and only core from the list
* Add support for stm32wl55 chip family
 2021-06-16 15:12:07 +02:00
Ulf Lilleengen
49fad2de8a Use correct frequencies for timers 2021-06-15 16:07:23 +02:00
Ulf Lilleengen
5e1b0a5398 Add wb55 clocks 2021-06-14 11:41:02 +02:00
Ulf Lilleengen
95532726b2 Add minimal RCC impls for L4 and F4 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
952f525af5 Provide a way for a peripheral to query its clock frequency 
Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
6c7fd3e3c4 Refactor 2021-06-11 16:21:51 +02:00
Ulf Lilleengen
8dd3ddd228 Special handling for timers instead 2021-06-10 09:52:57 +02:00
Ulf Lilleengen
0a9022d59f Enable timer clock in RCC on timer start 
* Moves the tim2-specific code into macro which always uses TIM2
* For peripherals without clock specified, attempt to locate enable and
  reset registers in the RCC block matching the peripheral name. This
  could be useful for peripherals where deducing the clock name might
  not be feasible, but it remains to be tested with more chip families
  to see if it is sufficiently accurate.
 2021-06-10 09:37:30 +02:00
Dario Nieuwenhuis
5b8ac447f2 stm32-metapac: add new codegen, allows pregenerating the entire pac 2021-06-10 02:33:38 +02:00
Ulf Lilleengen
9a2adec584 Make RCC lookup optional 2021-06-09 19:33:29 +02:00
Ulf Lilleengen
a92d6a372b Cleanup and fix l4s 2021-06-09 13:50:04 +02:00
Ulf Lilleengen
bd759510ba Generate clock peripherals for all peripherals with register block 
Infers clock for a peripheral using the selected clock as a prefix, in
order to work with split registers
 2021-06-09 13:40:34 +02:00
Ulf Lilleengen
f7394e56ef Handle other L4 variants 2021-06-08 17:37:41 +02:00
Ulf Lilleengen
459049d604 Workaround for L4 2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ee47a3e802 Add workaround for STM32H7 2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ee3b82b743 Auto generate SPI v2 clock enable 
Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral.

Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.
 2021-06-08 17:20:29 +02:00
Dario Nieuwenhuis
b65c3c7160 stm32-metapac: Do not generate cfgs metadata 2021-06-07 05:13:30 +02:00
Dario Nieuwenhuis
3be49d3e79 fmt: Add dunmy use to avoid "unused variable" errors when no log is enabled. 2021-06-07 03:21:37 +02:00
Bob McWhirter
d75bf143eb Remove the exti_interrupts table. 2021-06-03 14:18:58 -04:00
Bob McWhirter
fe47f781be Migrate exti_irq stuff to macro tables. 2021-06-03 13:35:27 -04:00
Bob McWhirter
6958091b50 Move DAC, I2C, SPI and RNG to macro-tables. 2021-06-03 13:12:38 -04:00
Bob McWhirter
d4d914ea50 Remove the Option around the pins Vec. 2021-06-03 13:12:38 -04:00
Bob McWhirter
be180c1c52 Create the new peripheral_pins! macro table. 2021-06-03 13:12:38 -04:00
Dario Nieuwenhuis
2aa836b068 Fix L4+ family cfg 2021-06-01 15:57:25 +02:00
Dario Nieuwenhuis
1f2097ab11 cortex-m-rt is not a build dep 2021-06-01 15:53:44 +02:00
Dario Nieuwenhuis
60f12c78dd Add resolver=2 2021-05-31 02:43:59 +02:00
Dario Nieuwenhuis
d8e4421fc6 Add stm32-metapac crate, with codegen in rust 2021-05-31 02:40:58 +02:00