fb697a2657
Updates
2021-09-15 12:46:20 +02:00
7ad6280e65
Add HAL for SubGhz peripheral for STM32 WL series
...
Based on the HAL from stm32wl, the peripheral driver has been
modified to fit into embassy, using the embassy APIs, providing
operation of the radio peripheral.
The initial version does not offer any async APIs, but the example
shows how the radio IRQ can be used to perform async TX of the radio.
2021-09-02 10:39:56 +02:00
e2f71ffbbd
Add support for STM32G0
2021-08-20 00:15:11 +02:00
174c51f097
stm32/metapac: check GPIO RCC regs are always found.
2021-08-19 23:59:50 +02:00
2c992f7010
stm32: move dbgmcu stuff to toplevel config setting, defaulting to true.
2021-08-19 23:50:19 +02:00
9f51f9a170
stm32/wl: add stub APB3 to get it to build.
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Completely untested.
2021-08-19 22:51:41 +02:00
637fcdd316
stm32/rcc: update for new version naming
2021-08-19 22:17:45 +02:00
61409e2fb6
Add example for STM32WL55
2021-08-17 16:22:47 +02:00
41aaff95f8
stm32h7: Use unwrap!
2021-08-05 22:39:59 +02:00
e44acd0d56
stm32f4: Use unwrap! where possible
2021-08-05 22:39:59 +02:00
f4971fbb79
Further work sharing config for example and removing duplicated code.
2021-08-04 13:39:02 -04:00
03f15d3a60
Remove builders from Config(s) and examples.
2021-08-04 11:32:39 -04:00
88c11a653c
Formatting fixes.
2021-08-03 14:12:11 -04:00
d7409d63e8
Enhance Rcc configuration to be more fluentish.
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Clean up H7 examples to remove all vegan HALs and PACs.
2021-08-03 13:57:18 -04:00
3835278567
Merge pull request #321 from thalesfragoso/f4-pll
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F4 PLL
2021-07-31 11:08:46 +02:00
21e3acaa00
stm32: Use build.rs to generate a more coarse feature
2021-07-31 02:52:26 -03:00
0421c57bd6
F4: Add PWR configuration to PLL
2021-07-29 18:43:15 -03:00
5cfb9adad8
f4-pll: Add max values per chip
2021-07-29 18:43:15 -03:00
e7714983b3
f4-rcc: Add option to enable debug_wfe and add hello example
2021-07-29 18:43:15 -03:00
5abaf8e9d6
Start working on the F4 PLL
2021-07-29 18:43:13 -03:00
9342497132
stm32wl55: Use Dbgmcu::enable_all
2021-07-29 17:38:40 +02:00
cad43587e6
stm32l0: Use embassy::main for examples
2021-07-29 17:37:32 +02:00
2a4890165d
stm32f0: Enable debug access in low power modes
2021-07-29 15:35:23 +02:00
7bfb763e09
Rename embassy-extras to embassy-hal-common
2021-07-29 13:44:51 +02:00
2f08c7ced5
stm32: Allow for RccPeripheral without reset field
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This fix build on F0, since it doesn't have DMARST. This change makes
RccPeripheral::reset a no-op on peripherals where a reset field couldn't
be found
2021-07-15 13:25:51 -03:00
06e899b14c
Adjust to DMA1EN in the rcc for l0.
2021-07-13 10:09:35 -04:00
13975a0818
Try to improve H7 clockstuff.
2021-07-13 10:09:35 -04:00
c2f595b26a
F0: Fix missing apb2 clock
2021-07-03 02:12:22 -03:00
c53ab325c1
Wire up DMA with USART v1.
2021-06-29 11:01:57 -04:00
409884be2a
Add F0 RCC
2021-06-24 19:21:56 -03:00
5a4e3ceb88
Update stm32-data (adds DBGMCU to all chips)
2021-06-21 01:38:59 +02:00
56c5218292
Prescaler 1 means divide by 3 on WL55
2021-06-16 16:21:16 +02:00
383beb37b3
Rename from wl55 to wl5x and enable debug wfe
2021-06-16 16:07:21 +02:00
b6a8703698
Add support for generating PAC for dual cores
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* Chips that have multiple cores will be exposed as chipname_corename,
i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
and pick the first and only core from the list
* Add support for stm32wl55 chip family
2021-06-16 15:12:07 +02:00
8ae4f47d3d
Fix compile
2021-06-15 16:44:00 +02:00
49fad2de8a
Use correct frequencies for timers
2021-06-15 16:07:23 +02:00
4b406dd107
Remove default rcc impl
2021-06-14 20:24:51 +02:00
5e1b0a5398
Add wb55 clocks
2021-06-14 11:41:02 +02:00
ee9f67fa01
Add common types
2021-06-14 11:33:11 +02:00
a2da2a6db2
Remove unused l0 code
2021-06-14 11:33:11 +02:00
95532726b2
Add minimal RCC impls for L4 and F4
2021-06-14 11:33:11 +02:00
a13e07625f
Add ... c1?
2021-06-14 11:33:11 +02:00
0b52731897
Add clocks for h7
2021-06-14 11:33:11 +02:00
2c63393c9e
Add Clock type per RCC family
2021-06-14 11:33:11 +02:00
952f525af5
Provide a way for a peripheral to query its clock frequency
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Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
2021-06-14 11:33:11 +02:00
1bb7123156
Add examples for STM32L0
2021-06-09 23:09:48 +02:00
ed29d82071
Use critical_section
2021-06-08 17:20:29 +02:00
ee3b82b743
Auto generate SPI v2 clock enable
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Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral.
Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.
2021-06-08 17:20:29 +02:00
a63388874a
Update after name fix
2021-06-07 14:06:54 +02:00
1cd2c55b7c
Fix stm32l0 build
2021-06-07 12:19:09 +02:00
