Commit Graph

2499 Commits

Author SHA1 Message Date
huntc
df5ba727f2 Further API simplification for the single seq scenario 2022-02-05 08:05:23 +11:00
huntc
81d31e43eb Removed unrequired clone 2022-02-04 19:18:10 +11:00
huntc
3b2beddc7a Forgot to expose the stop method 2022-02-04 19:14:24 +11:00
huntc
965a5f2c3f Introduced the SingleSequencer and a more complex Sequencer 2022-02-04 19:11:15 +11:00
huntc
9e36ede363 Small correction to times 2022-02-04 16:48:26 +11:00
huntc
e9e4d058d1 Revert the use of forever 2022-02-04 16:39:14 +11:00
huntc
81f98c32aa Update another example 2022-02-04 16:34:25 +11:00
huntc
fe5501293f Expose PWM 2022-02-04 16:26:23 +11:00
huntc
25be00878c Doco correction 2022-02-04 15:55:04 +11:00
huntc
1af6b23f97 Introduces a Sequences struct 2022-02-04 13:04:55 +11:00
huntc
bc7266394d Clarify why we need the mut buffer 2022-02-04 11:48:08 +11:00
bors[bot]
abd21ad139
Merge #595
595: stm32f3: fix nonexistent cfg tests r=Dirbaio a=unrelentingtech

The rcc code was taken from stm32-rs which uses 'x' features, but embassy uses features with full chip names.

Add these 'x' wildcards as cfgs and use them in rcc. They will be useful for USB #580 too.

---

I don't have any F3 boards, so this is not tested. But the original cfg clearly doesn't look right…

Co-authored-by: Greg V <greg@unrelenting.technology>
2022-02-02 20:03:21 +00:00
Greg V
8bb41a3281 stm32f3: fix nonexistent cfg tests
The rcc code was taken from stm32-rs which uses 'x' features, but
embassy uses features with full chip names.

Add these 'x' wildcards as cfgs and use them in rcc.
They will be useful for USB too.
2022-02-02 22:53:03 +03:00
huntc
986295998a Some more doco 2022-01-30 16:26:09 +11:00
huntc
1c67bd4643 Revert "Own the sequence buffer"
This reverts commit 482389a691.
2022-01-30 16:21:23 +11:00
huntc
482389a691 Own the sequence buffer
This approach owns the sequence buffers which, while introducing an extra move, it eliminates the need to guard the lifetime of the sequence buffer. Given ownership, the buffer will be retained until the PWM sequence task is stopped.
2022-01-29 18:01:06 +11:00
huntc
9ac52a768b Now permits sequences to be mutated subsequently 2022-01-28 16:32:58 +11:00
huntc
8e9f448866 Doc tidying 2022-01-28 13:43:36 +11:00
huntc
12ce024574 Make the sequence a little nicer to pass around 2022-01-28 13:38:20 +11:00
huntc
47aeab152f PWM WS2812B example and per sequence config
Demonstrates how to set the colour of a WS2812B to blue using PWM, and the use of multiple sequences along with their own config. This required an API change.
2022-01-28 11:20:04 +11:00
Dario Nieuwenhuis
0719b05d63 traits: migrate Delay to embedded-hal 1.0+async, remove Rng and Flash. 2022-01-27 00:08:02 +01:00
bors[bot]
d76cd5ceaf
Merge #592
592: Initial work on unstable-trait feature for stm32 r=lulf a=lulf

Implements async traits for exti for now. 

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-01-26 22:01:46 +00:00
Ulf Lilleengen
c8347fafb0 Add unstable-traits for stm32 to CI 2022-01-26 22:49:45 +01:00
Ulf Lilleengen
4032fc0655 Support unstable-trait feature for stm32 2022-01-26 22:39:06 +01:00
bors[bot]
cd36e3f733
Merge #589
589: stm32/i2c: allow empty writes r=Dirbaio a=darkwater

The Senseair Sunrise CO2 sensor expects a wake-up packet in the form of (START, address, STOP), which looks like a `write(addr, &[])`, but this assertion prevents sending that.

I'm not sure why the assertion is there. Sending empty packets works fine in my limited testing, at least.

Co-authored-by: Sam Lakerveld <dark@dark.red>
2022-01-25 16:19:46 +00:00
Sam Lakerveld
3fc54236ea
stm32/i2c: allow empty transfers with async api 2022-01-25 16:28:49 +01:00
bors[bot]
a950266a75
Merge #590
590: Stop PWM before assigning the new sequence r=huntc a=huntc

I had introduced a small bug in my last PR where I assigned the sequence before stopping the PWM. I now stop the PWM before doing that now.

Also, corrected a math comment.

Co-authored-by: huntc <huntchr@gmail.com>
2022-01-25 06:46:37 +00:00
huntc
c9f29534d6 Stop PWM before assigning the new sequence
I had introduced a small bug in my last PR where I assigned the sequence before stopping the PWM. I now stop the PWM before doing that now.

Also, corrected a math comment.
2022-01-25 16:51:24 +11:00
bors[bot]
0549a9dbaa
Merge #585
585: Permit many sequences to be passed r=huntc a=huntc

Sequences are now passed in via the start method to avoid having to stop the PWM and restart it. Sequences continue to be constrained with the same lifetime of the Pwm struct itself. The pwm_sequence example has been extended to illustrate multiple sequences being passed around.

Co-authored-by: huntc <huntchr@gmail.com>
2022-01-24 21:42:01 +00:00
huntc
48afef28a0 Strengthen the borrow
The start method is now safe. Because it has the potential of borrowing the sequence and mutating itself, the sequence must outlive the Pwm struct.
2022-01-24 17:22:35 +11:00
bors[bot]
917b0ea9b1
Merge #587
587: Update stm32-data r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-01-24 01:28:16 +00:00
Dario Nieuwenhuis
c2eb6d6ddf Update stm32-data 2022-01-24 02:19:10 +01:00
bors[bot]
982f5a9a19
Merge #586
586: stm32: add `time-driver-any` cargo feature that automatically picks one. r=Dirbaio a=Dirbaio

Most of the time you don't care which one gets used, so this is easier! :) 

It also helps for building docs for all chips, it reduces the feature changes needed.

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-01-24 00:17:50 +00:00
Dario Nieuwenhuis
6bf935402f stm32/ci: add stm32f410tb, time-driver-any 2022-01-24 01:07:49 +01:00
Dario Nieuwenhuis
a8580ec78a stm32/rcc: fix stm32f410 2022-01-24 00:50:35 +01:00
Dario Nieuwenhuis
533ceb707c stm32: add tim4, tim5 support for time-driver (stm32f410 doesn't have tim2, tim3) 2022-01-24 00:50:10 +01:00
Dario Nieuwenhuis
79f60adbfb stm32: add time-driver-any cargo feature that automatically picks one available timer. 2022-01-24 00:24:53 +01:00
huntc
7598b8a40f Permit many sequences to be passed
Sequences are now passed in via the start method to avoid having to stop the PWM and restart it. Sequences continue to be constrained with the same lifetime of the Pwm object itself. The pwm_sequence example has been extended to illustrate multiple sequences being passed around.
2022-01-23 16:29:52 +11:00
bors[bot]
6b0cb0609b
Merge #581
581: stm32: expose all functionality as inherent methods. r=Dirbaio a=Dirbaio

This is the previous step to implementing both the embedded-hal 0.2 and embedded-hal 1.0 + embedded-hal-async traits.

The equivalent in nrf was done in #552 

- Removes need for `unwrap` in gpio.
- Removes need for `use embedded_hal::whatever` in all cases.

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-01-19 20:47:07 +00:00
Dario Nieuwenhuis
889d757ab8 stm32/spi: expose all functionality as inherent methods. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
3d27a0e7cb stm32/dma: make lowlevel api take ptrs instead of slices. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
97ab859f00 stm32/i2c: expose all functionality as inherent methods. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
c949519714 stm32/usart: expose all functionality as inherent methods. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
98f24bf819 examples/stm32l0: cleanup 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
ade44e91c4 stm32/exti: add wait_for_high, wait_for_low. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
b526addf7b stm32/exti: expose all functionality as inherent methods. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
58fc64722c stm32/gpio: expose all functionality as inherent methods. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
52e156b429 stm32: use critical_section instead of cortex_m::interrupt 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
ecda57dff1 stm32: remove unused .pep8 file 2022-01-19 17:59:55 +01:00
bors[bot]
071b034a5d
Merge #582
582: Make advanced timer trait not require general purpose timer trait as … r=Dirbaio a=matoushybl

…the timers are too different.

When developing pwm driver, I originally used T: GeneralPurpose16bitTimer as it could support both GP timers and advanced timer, but advanced timer requires further modifications in registers accessible only in it (BDTR - bit AOE).

This PR makes advanced timers depend on Basic16bitTimer instead, which should hopefully improve type safety and allow for better timer drivers that can distinguish between advanced timers and general purpose ones.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-01-19 16:45:56 +00:00