Liam Murphy
e6d0dba5ca
Write bits directly to intenset/clr + shorts
2021-06-29 14:37:37 +10:00
Liam Murphy
87ca902e44
Handle differences between PACs
2021-06-29 13:04:05 +10:00
Liam Murphy
0c0597f775
Don't include extended timer support on chips without it
2021-06-29 12:07:10 +10:00
Liam Murphy
94e13ef053
Fix Cc::event_compare
2021-06-29 11:39:50 +10:00
Liam Murphy
e5a5031f20
Get rid of the TODO about variant names, stop the timer before setting BITMODE and set a default frequency.
2021-06-29 11:29:32 +10:00
Liam Murphy
e7addf094b
Fix Cc::wait never resolving and refactor some APIs
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I think the interrupt was getting immediately re-triggered as soon as the handler exited, so I disabled the interrupt in the handler.
2021-06-29 10:33:41 +10:00
Liam Murphy
02781ed744
Add an nRF Timer driver
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Resolves #189
2021-06-26 17:58:36 +10:00
Dario Nieuwenhuis
e6d6e82e54
Merge pull request #257 from embassy-rs/rp-clocks
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rp: fixes and add SPi
2021-06-25 06:43:22 +02:00
Dario Nieuwenhuis
88bc2972f6
rp/spi: add write-only spi driver
2021-06-25 06:24:14 +02:00
Dario Nieuwenhuis
9cf1d5b29c
rp/clocks: fix wrong PLL setup
2021-06-25 06:24:14 +02:00
Dario Nieuwenhuis
c7c897bb72
rp/gpio: add infallible inherent methods
2021-06-25 06:24:14 +02:00
Dario Nieuwenhuis
a35c8561c7
Merge pull request #256 from embassy-rs/rp-clocks
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rp: clock setup
2021-06-25 03:51:39 +02:00
Dario Nieuwenhuis
5a6384d199
rp: clock setup
2021-06-25 03:38:21 +02:00
Thales
e1880a19df
Merge pull request #254 from thalesfragoso/f0-rcc
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F0 rcc
2021-06-24 20:39:51 -03:00
Thales Fragoso
013792b944
Separate exti into v1 and v2
2021-06-24 20:28:06 -03:00
Thales Fragoso
1c33a3b94c
#[cfg] exti
2021-06-24 19:41:04 -03:00
Thales Fragoso
210104e6dc
Remove unused gpio_af from codegen
2021-06-24 19:23:51 -03:00
Thales Fragoso
409884be2a
Add F0 RCC
2021-06-24 19:21:56 -03:00
Thales Fragoso
797534d1a6
Update features to include F0
2021-06-22 14:41:42 -03:00
Dario Nieuwenhuis
9e5406f761
Merge pull request #252 from thalesfragoso/net-resources
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net: Make the user pass in the StackResources in init
2021-06-21 01:49:32 +02:00
Dario Nieuwenhuis
5a4e3ceb88
Update stm32-data (adds DBGMCU to all chips)
2021-06-21 01:38:59 +02:00
Thales Fragoso
aca0fb1065
net: Make the user pass in the StackResources in init
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By having the user pass in the resources, we can make them generic, this way
the user can choose the size of the individual resources
2021-06-20 17:15:18 -03:00
Dario Nieuwenhuis
06d69a8028
Merge pull request #251 from embassy-rs/net-fix
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net/tcp: Fix panic when consuming 0 bytes at EOF
2021-06-18 02:06:41 +02:00
Dario Nieuwenhuis
d94feb9fcd
net/tcp: Fix panic when consuming 0 bytes at EOF
2021-06-18 01:58:14 +02:00
Dario Nieuwenhuis
0d1ae0a01e
Merge pull request #247 from thalesfragoso/eth-v2
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Eth v2
2021-06-16 16:55:39 +02:00
Thales Fragoso
098ce6e740
stm32h7: Add ethernet example
2021-06-16 16:48:35 +02:00
Thales Fragoso
77546825a1
stm32: Make vcell dependency optional
2021-06-16 16:48:35 +02:00
Thales Fragoso
598201bff3
eth-v2: Make embassy-net optional
2021-06-16 16:48:35 +02:00
Thales Fragoso
3396a51938
net: Add features for pool size and remove unwrap on smoltcp device
2021-06-16 16:48:35 +02:00
Thales Fragoso
6cecc6d4b5
eth-v2: Get hclk frequency from clock singleton
2021-06-16 16:48:35 +02:00
Thales Fragoso
f7e1f262af
eth-v2: Enable source address filtering
2021-06-16 16:48:35 +02:00
Thales Fragoso
ffc19a54d6
eth-v2: Fix bug in Rx descriptors and add docs art
2021-06-16 16:48:35 +02:00
Thales Fragoso
6daa55a897
eth-v2: Fix setting the registers for the descriptors
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Also, the interrupts are set to 1 to clear, the manual could have helped
with that one...
2021-06-16 16:48:35 +02:00
Thales Fragoso
0b42e12604
eth-v2: Fix off by one bug
2021-06-16 16:48:35 +02:00
Thales Fragoso
54ad2a41f1
eth-v2: Work around missing AF for REF_CLK
2021-06-16 16:48:35 +02:00
Thales Fragoso
0c837f07c0
eth-v2: Enable clocks in new
2021-06-16 16:48:35 +02:00
Thales Fragoso
e039c7c42c
eth-v2: Remove Instance trait
2021-06-16 16:48:35 +02:00
Thales Fragoso
05a239faf6
eth-v2: Implement embassy-net's Device Trait and fix Drop
2021-06-16 16:48:35 +02:00
Thales Fragoso
4cffa200bd
eth: Add lan8742a PHY
2021-06-16 16:48:35 +02:00
Thales Fragoso
46e1bae9e3
eth-v2: Start Ethernet peripheral implementation
2021-06-16 16:48:35 +02:00
Dario Nieuwenhuis
6386c34079
Merge pull request #250 from lulf/dual-core
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Add support for generating PAC for dual cores
2021-06-16 16:46:01 +02:00
Ulf Lilleengen
a4ea08f89f
Update submodule
2021-06-16 16:31:12 +02:00
Ulf Lilleengen
56c5218292
Prescaler 1 means divide by 3 on WL55
2021-06-16 16:21:16 +02:00
Ulf Lilleengen
383beb37b3
Rename from wl55 to wl5x and enable debug wfe
2021-06-16 16:07:21 +02:00
Ulf Lilleengen
b6a8703698
Add support for generating PAC for dual cores
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* Chips that have multiple cores will be exposed as chipname_corename,
i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
and pick the first and only core from the list
* Add support for stm32wl55 chip family
2021-06-16 15:12:07 +02:00
Dario Nieuwenhuis
927be50109
Merge pull request #249 from embassy-rs/nrf-pacs
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nrf: use released nrf52805-pac, nrf52820-pac
2021-06-15 23:12:55 +02:00
Dario Nieuwenhuis
76ae9e0e7c
nrf: use released nrf52805-pac, nrf52820-pac
2021-06-15 22:25:37 +02:00
Dario Nieuwenhuis
c9bf039cae
Merge pull request #248 from lulf/add-timer-frequencies
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Add separate fields for timer frequencies
2021-06-15 17:29:48 +02:00
Ulf Lilleengen
8ae4f47d3d
Fix compile
2021-06-15 16:44:00 +02:00
Ulf Lilleengen
49fad2de8a
Use correct frequencies for timers
2021-06-15 16:07:23 +02:00
