174 lines
4.5 KiB
Rust
174 lines
4.5 KiB
Rust
#![macro_use]
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pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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use futures::future::join3;
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use super::*;
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impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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pub(super) async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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{
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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let request = self.txdma.request();
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let dst = T::regs().tx_ptr();
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let f = self.txdma.write(request, write, dst);
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_cstart(true);
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});
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}
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f.await;
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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Ok(())
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}
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pub(super) async fn read_dma_u8(&mut self, read: &mut [u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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Rx: RxDmaChannel<T>,
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{
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(true);
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});
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}
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let clock_byte_count = read.len();
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let rx_request = self.rxdma.request();
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let rx_src = T::regs().rx_ptr();
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let rx_f = self.rxdma.read(rx_request, rx_src, read);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().tx_ptr();
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let clock_byte = 0x00;
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let tx_f = self
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.txdma
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.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_cstart(true);
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});
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}
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join3(tx_f, rx_f, Self::wait_for_idle()).await;
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(false);
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reg.set_txdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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Ok(())
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}
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pub(super) async fn read_write_dma_u8(
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&mut self,
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read: &mut [u8],
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write: &[u8],
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) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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Rx: RxDmaChannel<T>,
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{
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assert!(read.len() >= write.len());
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self.set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(true);
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});
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// Flush the read buffer to avoid errornous data from being read
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while T::regs().sr().read().rxp() {
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let _ = T::regs().rxdr().read();
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}
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}
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let rx_request = self.rxdma.request();
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let rx_src = T::regs().rx_ptr();
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let rx_f = self
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.rxdma
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.read(rx_request, rx_src, &mut read[0..write.len()]);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().tx_ptr();
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let tx_f = self.txdma.write(tx_request, write, tx_dst);
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_cstart(true);
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});
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}
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join3(tx_f, rx_f, Self::wait_for_idle()).await;
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(false);
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reg.set_txdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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Ok(())
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}
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async fn wait_for_idle() {
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unsafe {
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while !T::regs().sr().read().txc() {
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// spin
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}
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while T::regs().sr().read().rxplvl().0 > 0 {
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// spin
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}
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}
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}
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}
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