2023-06-12 13:27:51 +02:00
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#![no_std]
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// This must go FIRST so that all the other modules see its macros.
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pub mod fmt;
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2023-05-02 13:16:48 +02:00
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use core::mem::MaybeUninit;
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2023-06-14 00:12:34 +02:00
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use core::sync::atomic::{compiler_fence, Ordering};
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2023-05-02 13:16:48 +02:00
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2023-06-12 13:27:51 +02:00
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use cmd::CmdPacket;
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2023-05-27 22:05:23 +02:00
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use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
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2023-06-12 13:27:51 +02:00
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use embassy_stm32::interrupt;
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2023-06-12 15:44:30 +02:00
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use embassy_stm32::interrupt::typelevel::Interrupt;
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2023-06-17 19:00:33 +02:00
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use embassy_stm32::ipcc::{Config, Ipcc, ReceiveInterruptHandler, TransmitInterruptHandler};
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2023-06-12 13:27:51 +02:00
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use embassy_stm32::peripherals::IPCC;
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2023-05-15 11:25:02 +02:00
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use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
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use embassy_sync::channel::Channel;
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2023-06-08 17:26:47 +02:00
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use embassy_sync::signal::Signal;
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2023-06-12 13:27:51 +02:00
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use evt::{CcEvt, EvtBox};
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use tables::{
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BleTable, DeviceInfoTable, Mac802_15_4Table, MemManagerTable, RefTable, SysTable, ThreadTable, TracesTable,
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WirelessFwInfoTable,
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};
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use unsafe_linked_list::LinkedListNode;
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2023-05-02 13:16:48 +02:00
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2023-06-08 17:26:47 +02:00
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pub mod ble;
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pub mod channels;
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pub mod cmd;
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pub mod consts;
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pub mod evt;
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pub mod mm;
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pub mod shci;
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pub mod sys;
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2023-06-12 13:27:51 +02:00
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pub mod tables;
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2023-06-08 17:26:47 +02:00
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pub mod unsafe_linked_list;
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2023-05-02 13:16:48 +02:00
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#[link_section = "TL_REF_TABLE"]
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pub static mut TL_REF_TABLE: MaybeUninit<RefTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_DEVICE_INFO_TABLE: MaybeUninit<DeviceInfoTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_BLE_TABLE: MaybeUninit<BleTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_THREAD_TABLE: MaybeUninit<ThreadTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_SYS_TABLE: MaybeUninit<SysTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_MEM_MANAGER_TABLE: MaybeUninit<MemManagerTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_TRACES_TABLE: MaybeUninit<TracesTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_MAC_802_15_4_TABLE: MaybeUninit<Mac802_15_4Table> = MaybeUninit::uninit();
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2023-06-08 17:26:47 +02:00
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#[link_section = "MB_MEM2"]
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static mut FREE_BUF_QUEUE: MaybeUninit<LinkedListNode> = MaybeUninit::uninit();
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// Not in shared RAM
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static mut LOCAL_FREE_BUF_QUEUE: MaybeUninit<LinkedListNode> = MaybeUninit::uninit();
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2023-05-12 11:26:46 +02:00
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2023-05-26 12:26:58 +02:00
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#[allow(dead_code)] // Not used currently but reserved
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2023-06-08 17:26:47 +02:00
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#[link_section = "MB_MEM2"]
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static mut TRACES_EVT_QUEUE: MaybeUninit<LinkedListNode> = MaybeUninit::uninit();
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2023-05-02 13:16:48 +02:00
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2023-06-08 17:26:47 +02:00
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type PacketHeader = LinkedListNode;
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const TL_PACKET_HEADER_SIZE: usize = core::mem::size_of::<PacketHeader>();
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const TL_EVT_HEADER_SIZE: usize = 3;
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const TL_CS_EVT_SIZE: usize = core::mem::size_of::<evt::CsEvt>();
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2023-05-26 12:26:58 +02:00
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-02 13:16:48 +02:00
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static mut CS_BUFFER: MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + TL_CS_EVT_SIZE]> =
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MaybeUninit::uninit();
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2023-05-26 12:26:58 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-02 13:16:48 +02:00
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static mut EVT_QUEUE: MaybeUninit<LinkedListNode> = MaybeUninit::uninit();
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2023-05-15 11:25:02 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-02 13:16:48 +02:00
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static mut SYSTEM_EVT_QUEUE: MaybeUninit<LinkedListNode> = MaybeUninit::uninit();
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2023-05-25 17:39:43 +02:00
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#[link_section = "MB_MEM2"]
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2023-06-08 17:26:47 +02:00
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pub static mut SYS_CMD_BUF: MaybeUninit<CmdPacket> = MaybeUninit::uninit();
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/**
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* Queue length of BLE Event
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* This parameter defines the number of asynchronous events that can be stored in the HCI layer before
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* being reported to the application. When a command is sent to the BLE core coprocessor, the HCI layer
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* is waiting for the event with the Num_HCI_Command_Packets set to 1. The receive queue shall be large
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* enough to store all asynchronous events received in between.
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* When CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE is set to 27, this allow to store three 255 bytes long asynchronous events
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* between the HCI command and its event.
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* This parameter depends on the value given to CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE. When the queue size is to small,
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* the system may hang if the queue is full with asynchronous events and the HCI layer is still waiting
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* for a CC/CS event, In that case, the notification TL_BLE_HCI_ToNot() is called to indicate
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* to the application a HCI command did not receive its command event within 30s (Default HCI Timeout).
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*/
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const CFG_TLBLE_EVT_QUEUE_LENGTH: usize = 5;
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const CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE: usize = 255;
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const TL_BLE_EVENT_FRAME_SIZE: usize = TL_EVT_HEADER_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE;
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const fn divc(x: usize, y: usize) -> usize {
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((x) + (y) - 1) / (y)
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}
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const POOL_SIZE: usize = CFG_TLBLE_EVT_QUEUE_LENGTH * 4 * divc(TL_PACKET_HEADER_SIZE + TL_BLE_EVENT_FRAME_SIZE, 4);
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2023-05-25 17:39:43 +02:00
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-26 12:26:58 +02:00
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static mut EVT_POOL: MaybeUninit<[u8; POOL_SIZE]> = MaybeUninit::uninit();
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2023-05-25 17:39:43 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-26 12:26:58 +02:00
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static mut SYS_SPARE_EVT_BUF: MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + 255]> =
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2023-05-02 13:16:48 +02:00
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MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-25 17:39:43 +02:00
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static mut BLE_SPARE_EVT_BUF: MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + 255]> =
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MaybeUninit::uninit();
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2023-05-26 12:26:58 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-02 13:16:48 +02:00
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static mut BLE_CMD_BUFFER: MaybeUninit<CmdPacket> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM2"]
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2023-06-08 17:26:47 +02:00
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// fuck these "magic" numbers from ST ---v---v
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2023-05-02 13:16:48 +02:00
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static mut HCI_ACL_DATA_BUFFER: MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + 5 + 251]> = MaybeUninit::uninit();
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2023-06-08 17:26:47 +02:00
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/// current event that is produced during IPCC IRQ handler execution
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/// on SYS channel
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2023-06-12 13:27:51 +02:00
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static EVT_CHANNEL: Channel<CriticalSectionRawMutex, EvtBox, 32> = Channel::new();
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2023-06-08 17:26:47 +02:00
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/// last received Command Complete event
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static LAST_CC_EVT: Signal<CriticalSectionRawMutex, CcEvt> = Signal::new();
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2023-05-15 11:25:02 +02:00
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2023-06-12 13:27:51 +02:00
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static STATE: Signal<CriticalSectionRawMutex, ()> = Signal::new();
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2023-06-08 17:26:47 +02:00
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2023-06-12 13:27:51 +02:00
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pub struct TlMbox<'d> {
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2023-05-27 22:05:23 +02:00
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_ipcc: PeripheralRef<'d, IPCC>,
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2023-05-02 13:16:48 +02:00
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}
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2023-05-27 22:05:23 +02:00
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impl<'d> TlMbox<'d> {
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2023-06-12 13:27:51 +02:00
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pub fn init(
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2023-05-27 22:05:23 +02:00
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ipcc: impl Peripheral<P = IPCC> + 'd,
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2023-06-12 15:44:30 +02:00
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_irqs: impl interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_RX, ReceiveInterruptHandler>
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+ interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_TX, TransmitInterruptHandler>,
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2023-05-26 10:56:55 +02:00
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config: Config,
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2023-05-27 22:05:23 +02:00
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) -> Self {
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into_ref!(ipcc);
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2023-05-02 13:16:48 +02:00
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unsafe {
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2023-06-14 00:12:34 +02:00
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TL_REF_TABLE.as_mut_ptr().write_volatile(RefTable {
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device_info_table: TL_DEVICE_INFO_TABLE.as_ptr(),
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2023-05-02 13:16:48 +02:00
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ble_table: TL_BLE_TABLE.as_ptr(),
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thread_table: TL_THREAD_TABLE.as_ptr(),
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sys_table: TL_SYS_TABLE.as_ptr(),
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mem_manager_table: TL_MEM_MANAGER_TABLE.as_ptr(),
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traces_table: TL_TRACES_TABLE.as_ptr(),
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mac_802_15_4_table: TL_MAC_802_15_4_TABLE.as_ptr(),
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2023-06-14 00:12:34 +02:00
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// zigbee_table: TL_ZIGBEE_TABLE.as_ptr(),
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// lld_tests_table: TL_LLD_TESTS_TABLE.as_ptr(),
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// ble_lld_table: TL_BLE_LLD_TABLE.as_ptr(),
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2023-05-02 13:16:48 +02:00
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});
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2023-06-14 00:12:34 +02:00
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TL_SYS_TABLE
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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TL_DEVICE_INFO_TABLE
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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TL_BLE_TABLE
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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TL_THREAD_TABLE
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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TL_MEM_MANAGER_TABLE
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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TL_TRACES_TABLE
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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TL_MAC_802_15_4_TABLE
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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2023-06-14 00:17:10 +02:00
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// TL_ZIGBEE_TABLE
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// .as_mut_ptr()
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// .write_volatile(MaybeUninit::zeroed().assume_init());
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// TL_LLD_TESTS_TABLE
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// .as_mut_ptr()
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// .write_volatile(MaybeUninit::zeroed().assume_init());
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// TL_BLE_LLD_TABLE
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// .as_mut_ptr()
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// .write_volatile(MaybeUninit::zeroed().assume_init());
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2023-06-14 00:12:34 +02:00
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EVT_POOL
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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SYS_SPARE_EVT_BUF
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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BLE_SPARE_EVT_BUF
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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{
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BLE_CMD_BUFFER
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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HCI_ACL_DATA_BUFFER
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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CS_BUFFER
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.as_mut_ptr()
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.write_volatile(MaybeUninit::zeroed().assume_init());
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}
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2023-05-02 13:16:48 +02:00
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}
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2023-06-14 00:12:34 +02:00
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compiler_fence(Ordering::SeqCst);
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2023-05-27 22:05:23 +02:00
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Ipcc::enable(config);
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2023-05-02 13:16:48 +02:00
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2023-06-12 13:27:51 +02:00
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sys::Sys::enable();
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ble::Ble::enable();
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mm::MemoryManager::enable();
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2023-05-02 13:16:48 +02:00
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2023-05-26 10:56:55 +02:00
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// enable interrupts
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2023-06-12 15:44:30 +02:00
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interrupt::typelevel::IPCC_C1_RX::unpend();
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interrupt::typelevel::IPCC_C1_TX::unpend();
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2023-05-26 10:56:55 +02:00
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2023-06-12 15:44:30 +02:00
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unsafe { interrupt::typelevel::IPCC_C1_RX::enable() };
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unsafe { interrupt::typelevel::IPCC_C1_TX::enable() };
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2023-05-15 11:25:02 +02:00
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2023-06-12 13:27:51 +02:00
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STATE.reset();
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Self { _ipcc: ipcc }
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2023-05-02 13:16:48 +02:00
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}
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2023-06-08 17:26:47 +02:00
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/// Returns CPU2 wireless firmware information (if present).
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2023-05-02 13:16:48 +02:00
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pub fn wireless_fw_info(&self) -> Option<WirelessFwInfoTable> {
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let info = unsafe { &(*(*TL_REF_TABLE.as_ptr()).device_info_table).wireless_fw_info_table };
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2023-06-08 17:26:47 +02:00
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// Zero version indicates that CPU2 wasn't active and didn't fill the information table
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2023-05-02 13:16:48 +02:00
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if info.version != 0 {
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Some(*info)
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} else {
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None
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}
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}
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}
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