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0fe0bc60fe
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1306 Commits

Author SHA1 Message Date
anton smeenk
0fe0bc60fe Merge remote-tracking branch 'origin/master' into feature-i2c-slave 
# Conflicts:
#	examples/stm32g0/Cargo.toml
 2023-10-27 14:58:43 +02:00
anton smeenk
ce066e92e7 Arbitration lost test is working. Still some test failing 2023-10-27 14:54:06 +02:00
anton smeenk
70a64e8dcb I2c slave is working now. Todo: enable and test master write-read transaction 2023-10-25 21:25:38 +02:00
Dario Nieuwenhuis
a39ae12edc stm32/rcc: misc cleanups. 2023-10-23 17:36:21 +02:00
Dario Nieuwenhuis
0ef1cb29f7 stm32/rcc: merge wb into l4/l5. 2023-10-23 17:36:21 +02:00
Dario Nieuwenhuis
b9e13cb5d1 stm32/rcc: merge wl into l4/l5. 2023-10-23 00:31:36 +02:00
Dario Nieuwenhuis
412bcad2d1 stm32: rename HSI16 -> HSI 2023-10-22 22:39:55 +02:00
anton smeenk
b1afd5141c Busy debugging the i2c slave 2023-10-21 12:11:32 +02:00
anton smeenk
007855423e Slave: write Starts working work in progress 2023-10-20 22:12:37 +02:00
Dion Dokter
5b3f75dc72 Merge branch 'master' into center-align 2023-10-20 14:17:55 +02:00
Ulf Lilleengen
035800bfbd
Merge pull request #2091 from embassy-rs/comment-memory-x 
docs: add linker script comments
 2023-10-19 08:19:42 +00:00
Ulf Lilleengen
c7803bb8f4
docs: add linker script comments 
Existing comment were outdated. Provide an example configuration
for using the softdevice with the nRF52 examples.
 2023-10-19 09:29:20 +02:00
Dario Nieuwenhuis
f20f170b1f stm32/rcc: refactor and unify f4 into f7. 2023-10-18 05:11:31 +02:00
Dario Nieuwenhuis
67010d123c stm32/rcc: refactor f7. 2023-10-18 05:01:11 +02:00
xoviat
bbd12c9372 stm32: update metapac 2023-10-17 20:31:44 -05:00
Dario Nieuwenhuis
b478640463 fix clocks in stm32wl rng example. 2023-10-17 15:57:09 +02:00
xoviat
683d5c3066
Merge pull request #2077 from xoviat/rcc 
stm32: update metapac
 2023-10-17 01:05:18 +00:00
xoviat
a3574e519a stm32: update metapac 2023-10-16 20:04:10 -05:00
Dario Nieuwenhuis
6e6df22979
Merge pull request #2075 from CBJamo/rosc_example 
Add example to show useage of rp2040 rosc
 2023-10-16 23:22:06 +00:00
Caleb Jamison
5a1393aa0b Add example to show useage of rp2040 rosc 2023-10-16 16:17:07 -04:00
Dániel Buga
40e4ca4751 Prepare embassy-net(/-driver,/-driver-channel) 0.2.0 2023-10-16 20:59:06 +02:00
Dario Nieuwenhuis
213b4c9dca time: add links key, release v0.1.5. 2023-10-16 20:11:35 +02:00
Dario Nieuwenhuis
18e96898ea stm32/rcc: unify L4 and L5. 2023-10-16 04:00:51 +02:00
Dario Nieuwenhuis
5c5e681819 stm32/rcc: add better support for L4/L4+ differences. 2023-10-16 03:23:43 +02:00
anton smeenk
9424379268 Added i2c_master test case in examples 2023-10-15 10:54:57 +02:00
xoviat
4a156df7a1 stm32: expand rcc mux to g4 and h7 2023-10-14 23:33:57 -05:00
Dario Nieuwenhuis
8a10948ce9 stm32/rcc: port L4 to the "flattened" API like h5/h7. 2023-10-15 03:08:49 +02:00
Adam Greig
0621e957a0
time: Update examples, tests, and other code to use new Timer::after_x convenience methods 2023-10-15 01:30:12 +01:00
Dario Nieuwenhuis
2e50bf667a
Merge pull request #2055 from kalkyl/usb-midi 
embassy-usb: Add MIDI class
 2023-10-14 23:10:25 +00:00
kalkyl
a57d383b1d embassy-usb: Add MIDI class 2023-10-14 04:20:59 +02:00
Dániel Buga
02d2c06b23 Release embassy-time 0.1.4 2023-10-12 18:14:33 +02:00
Dario Nieuwenhuis
66e399b5c6
Merge pull request #2035 from pbert519/stm_reset_and_enable 
STM32: combine RccPeripherals reset() and enable() to enable_and_reset()
 2023-10-12 14:09:13 +00:00
Ulf Lilleengen
01eb1a7339
Merge pull request #2033 from andresovela/stm32-add-timeout-to-i2c 
stm32: add timeout to I2C driver
 2023-10-12 10:44:27 +00:00
pbert
ecdd7c0e2f enable clock first 2023-10-12 11:04:44 +02:00
pbert
f65a96c541 STM32: combine RccPeripherals reset() and enable() to reset_and_enable() 2023-10-12 11:04:19 +02:00
Dario Nieuwenhuis
32b89eeba1 net: remove atomic-polyfill. 2023-10-12 02:07:26 +02:00
Andres Oliva
4cec4b0548 Remove more unused stuff 2023-10-11 23:52:26 +02:00
Dario Nieuwenhuis
b91d1eaca0 stm32/rcc: add LSE/LSI to all chips, add RTC to more chips. 2023-10-11 04:12:38 +02:00
Dario Nieuwenhuis
d0d0ceec6a stm32/rcc: rename HSE32 to HSE 2023-10-11 01:06:44 +02:00
Dario Nieuwenhuis
0cfa8d1bb5 stm32/rcc: use more PLL etc enums from PAC. 2023-10-11 00:12:33 +02:00
Andres Oliva
cd12c9cbce stm32: add timeout to I2C driver 2023-10-10 18:20:46 +02:00
Gabriel Górski
e62bf6a9fd Patch tests & examples 2023-10-09 13:46:56 +02:00
Dario Nieuwenhuis
6186fe0807 stm32/rcc: use PLL enums from PAC. 2023-10-09 02:48:22 +02:00
Dario Nieuwenhuis
85c6f23dcb
Merge pull request #2018 from jamesmunns/add-derives 
Add some uncontroversial derives to Error types
 2023-10-07 00:03:10 +00:00
Dario Nieuwenhuis
3bf8e4de5f
Merge pull request #2015 from willglynn/stm32u5_faster_clocks 
stm32: u5: implement >55 MHz clock speeds
 2023-10-06 23:38:15 +00:00
Dario Nieuwenhuis
3a8e0d4a27 stm32: implement MCO for all chips. 2023-10-07 01:15:24 +02:00
Matt Ickstadt
f01609036f h7: implement RTC and LSE clock configuration 2023-10-06 13:28:30 -05:00
James Munns
930b8f3495 Add some uncontroversial derives to Error types 2023-10-06 17:45:35 +02:00
Will Glynn
38e7709a24 stm32: u5: implement >55 MHz clock speeds 
This commit allows STM32U5 devices to operate at 160 MHz.

On STM32U5, MSIS can run at 48 MHz and HSE can reach 50 MHz. Faster
clocks require using PLL1's R output, though PLL1 can serve other
functions besides using the R output for the system clock. This commit
extracts a public `PllConfig` struct, primarily to place associated
constructors on that type, but also with an eye towards enabling the P
and Q outputs in a later commit.

STM32U5 PLLs have various frequency requirements on each stage: after
the `m` prescaler, after the `n` multiplier, and after the `r` divider.
This commit implements the associated checks as assertions.

This commit fixes clock calculation and PLL register configuration
errors in PLL initialization.

STM32U5 has a PWR peripheral which can be configured to push Vcore into
different voltage ranges. System clocks exceeding 55 MHz require range
2, and system clocks exceeding 110 MHz require range 1. This commit
adds `voltage_range` to `Config` and configures PWR as directed.

The voltage range implies different performance limits on various clock
signals, including inside a PLL. This commit implements voltage range
<-> frequency range checks as assertions, and extracts the
otherwise-repeated MSIS, HSI16, and HSE initialization into private
methods on `Config`.

STM32U5 frequencies above 55 MHz require using the PWR EPOD booster.
The EPOD booster requires configuring a second `m` term for PLL1,
`mboost`, such that it falls in a particular range. (Recall that >50
MHz cannot be reached without PLL1, so there is no scenario where EPOD
is needed but PLL1 is not.) This commit configures and enables the EPOD
booster automatically as required.
 2023-10-05 22:13:27 -05:00
xoviat
e1a0635ca3 stm32: update metapac and fix opamp ch 2023-10-04 16:15:08 -05:00