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203 Commits

Author SHA1 Message Date
xoviat
32fdd4c787 tests/stm32: fix rtc test 2023-08-08 20:33:24 -05:00
xoviat
6a73ab1afa stm32/l4: set rtc clock source in rcc 2023-08-08 19:58:03 -05:00
xoviat
6fc5c608f8 stm32/rtc: remove generics and segregate clock sel 2023-08-08 19:47:01 -05:00
xoviat
28618d12a1 stm32/rtc: restructure 2023-08-06 11:58:28 -05:00
xoviat
66c1712118 stm32/rtc: enable in rcc mod 2023-08-06 11:11:53 -05:00
Bartek
5fcebd28f4 Fix unlocking the backup domain when enabling LSE 
Set PWREN bit to enable the power interface clock before enabling access to the backup domain.
 2023-08-01 13:46:34 +09:30
Dario Nieuwenhuis
3aef5999d5
Merge pull request #1716 from xoviat/rcc-p 
stm32/rcc: extract and combine ahb/apb prescalers
 2023-07-30 20:43:54 +00:00
xoviat
a8a491212b stm32/rcc: cleanup merge 2023-07-30 10:18:54 -05:00
xoviat
2f18770e27 stm32/rcc: extract and combine ahb/apb prescalers 2023-07-30 09:52:30 -05:00
Scott Mabin
e0ce7fcde7 stm32f2 pll overflow with crystal 
With a large enough HSE input frequency, the vco clock calculation will
overflow a u32. Therefore, in this specific case we have to use the
inner value and cast to u64 to ensure the mul isn't clipped before
applying the divider.
 2023-07-30 01:00:53 +01:00
xoviat
c7c701b3e3 Merge branch 'main' of https://github.com/embassy-rs/embassy into hrtim 2023-07-28 17:18:22 -05:00
Dario Nieuwenhuis
036e6ae30c
Rename embassy-hal-common to embassy-hal-internal, document it's for internal use only. (#1700) 2023-07-28 13:23:22 +02:00
xoviat
270d1d59a0 stm32/rcc: use wpan default only for wpan 2023-07-24 18:25:15 -05:00
xoviat
1425dda0a7 stm32/rcc: fix minor issues 2023-07-24 17:19:45 -05:00
xoviat
bd60f003e0 stm32/rcc: move rcc logic from ipcc 2023-07-23 17:01:34 -05:00
xoviat
d42dff45de Merge branch 'main' of https://github.com/embassy-rs/embassy into hrtim 2023-07-22 14:49:31 -05:00
Phil Markgraf
3bae533066
Enable RTC on STM32WL chips (#1645) 
* Add clippy allow to not report if same then branch

* Support enabling RTC clock on STM32WL

* Add clippy allow to not report if same then branch

* Support enabling RTC clock on STM32WL

* Add rtc example for stm32wl

* Address code review feedback
 2023-07-15 13:40:23 +02:00
David Purser
69b4e898b3
Correctly calculate target VCO frequency from multipliers 2023-07-07 20:52:44 -05:00
Mathias
1255d8a8ce Merge branch 'main' of https://github.com/embassy-rs/embassy into embassy-stm32/rcc-rtc-l4 2023-07-05 12:36:42 +02:00
Dario Nieuwenhuis
eb57bb298f
Merge pull request #1617 from xoviat/const-rcc 
stm32/rcc: allow const-propagation
 2023-07-04 22:31:55 +00:00
xoviat
953c745ed8 stm32/rcc: allow const-propagation 2023-07-04 16:29:46 -05:00
Dario Nieuwenhuis
9c4df46c46 rustfmt. 2023-07-04 21:34:55 +02:00
Mathias
60b2f075dc Merge branch 'main' of https://github.com/embassy-rs/embassy into embassy-stm32/rcc-rtc-l4 2023-07-03 19:33:26 +02:00
xoviat
8141d53d94 Merge branch 'main' of https://github.com/embassy-rs/embassy into hrtim 2023-07-01 17:32:25 -05:00
Mathias
d372df7ddb L4: Switch to MSI to prevent problems with PLL configuration, and enable power to AHB bus clock to allow RTC to run 2023-07-01 12:16:23 +02:00
xoviat
6e13f5b387 rustfmt 2023-06-30 18:33:22 -05:00
Dario Nieuwenhuis
e892014b65 Update stm32-metapac, includes chiptool changes to use real Rust enums now. 2023-06-29 02:01:33 +02:00
Kevin Lannen
5666c56903 STM32G4: Add CRS support to RCC 
Create working CRS USB Example
 2023-06-28 16:53:16 -06:00
Dario Nieuwenhuis
ed493be869 stm32: update metapac, includes fix for OTG with 9 endpoints (H7) 2023-06-27 23:58:32 +02:00
Dario Nieuwenhuis
558918651e stm32: update stm32-metapac. 2023-06-19 03:22:12 +02:00
Kevin Lannen
c94ba84892 stm32g4: PLL: Add support for configuring PLL_P and PLL_Q 2023-06-14 10:44:51 -06:00
Carl St-Laurent
8ddeaddc67
Rename to follow ref manual and CubeIDE 2023-06-08 20:46:48 -04:00
Carl St-Laurent
4185c10bf8
Cleanup 2023-06-04 12:09:03 -04:00
Carl St-Laurent
ade46489f1
Added Vcore boost mode and Flash wait state 2023-06-04 11:57:42 -04:00
Carl St-Laurent
6fe853a7d3
Better comments 2023-06-04 10:58:44 -04:00
Carl St-Laurent
2f269f3256
stm32/rcc: Implement basic PLL support for STM32G4 series 2023-06-03 22:05:24 -04:00
bors[bot]
d28dc08f09
Merge #1486 
1486: feature(embassy-stm32): add RTC MUX selection to embassy-stm32 L4 family r=Dirbaio a=MathiasKoch

To select and setup LSE and/or LSI

Co-authored-by: Mathias <mk@blackbird.online>
 2023-05-25 20:13:27 +00:00
Mathias
181c4c5311 Add RTC MUX selection to embassy-stm32 L4 family, to select and setup LSE and/or LSI 2023-05-25 21:28:32 +02:00
Rasmus Melchior Jacobsen
963f3e3059 Align with updated stm32 metapac 2023-05-25 16:06:02 +02:00
Marco Pastrello
db2bc8783e Improve readability 2023-05-05 19:04:58 +02:00
Marco Pastrello
c37f86ff1c removes unecessary braces 2023-05-05 00:12:32 +02:00
Marco Pastrello
2dcbe75cca beautify 2023-05-04 23:51:42 +02:00
Marco Pastrello
5158014f3f PPLXTPRE is a bool. 
This flag for example permits the following clock tree
configuration on stm32f103r8

    let mut config = Config::default();
    config.rcc.hse = Some(Hertz(16_000_000));
    config.rcc.sys_ck = Some(Hertz(72_000_000));
    config.rcc.pclk1 = Some(Hertz(36_000_000));
    config.rcc.pclk2 = Some(Hertz(72_000_000));
    config.rcc.pllxtpre = true;

Init fails if pllxtpre is false.
 2023-05-04 22:59:52 +02:00
Marco Pastrello
1cc61dc68a Support PLLXTPRE switch. 
See figure 2. Clock tree page 12 DS5319 Rev 18
https://www.st.com/resource/en/datasheet/stm32f103cb.pdf
 2023-05-04 21:32:37 +02:00
bors[bot]
1fdce6e52a
Merge #1360 #1361 
1360: stm32/rcc: add i2s pll on some f4 micros r=Dirbaio a=xoviat

Adds the i2s pll on some f4 micros. 

1361: Executor: Replace unnecessary atomics in runqueue r=Dirbaio a=GrantM11235

Only the head pointer needs to be atomic. The `RunQueueItem` pointers are only loaded and stored, and never concurrently

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
Co-authored-by: Grant Miller <GrantM11235@gmail.com>
 2023-04-15 10:38:28 +00:00
xoviat
f395ec44e8 stm32/rcc: add pllsai clock 2023-04-14 21:28:27 -05:00
xoviat
650589ab3f stm32/rcc: add plli2s to Clocks and cfg directives 2023-04-14 16:30:36 -05:00
xoviat
c1d5f86871 stm32/rcc: fix warnings 2023-04-12 18:11:55 -05:00
xoviat
0289630fe4 stm32/rcc: add i2s pll on some f4 micros 2023-04-12 18:04:44 -05:00
Sebastian Goll
f3699e67b9 Fix typo in derivation of PLLP divisor 2023-04-12 02:07:31 +02:00