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Author SHA1 Message Date
Thales Fragoso
6ddc83029a i2c-v2: Simplify write_dma 2021-08-01 19:10:42 -03:00
Thales Fragoso
362f7efe99 i2c-v2: Implement write_dma and write_dma_vectored 2021-08-01 19:10:42 -03:00
Dario Nieuwenhuis
0a1da180d0
Merge pull request #335 from bgamari/no-build-core 
examples: Drop build-std = ["core"]
 2021-07-31 19:07:58 +02:00
Ben Gamari
3420cbf744 examples: Drop build-std = ["core"] 
Previously the cargo configurations of all of the example projects had
`build-std = ["core"]`, which forces compilation of `core` as a
code-size optimisation. However, this is strictly unnecessary and will
currently break for users who do not use `rustup` directly (e.g. nix
users).
 2021-07-31 13:01:15 -04:00
Dario Nieuwenhuis
3835278567
Merge pull request #321 from thalesfragoso/f4-pll 
F4 PLL
 2021-07-31 11:08:46 +02:00
Thales Fragoso
21e3acaa00 stm32: Use build.rs to generate a more coarse feature 2021-07-31 02:52:26 -03:00
Dario Nieuwenhuis
e9885a61f8
Merge pull request #329 from timokroeger/misc-stm32-fixes 
Misc stm32 fixes
 2021-07-30 18:15:50 +02:00
Thales Fragoso
16d5294817 Get rid of some warnings 2021-07-29 18:48:43 -03:00
Thales Fragoso
0421c57bd6 F4: Add PWR configuration to PLL 2021-07-29 18:43:15 -03:00
Thales Fragoso
5cfb9adad8 f4-pll: Add max values per chip 2021-07-29 18:43:15 -03:00
Thales Fragoso
e7714983b3 f4-rcc: Add option to enable debug_wfe and add hello example 2021-07-29 18:43:15 -03:00
Thales Fragoso
5abaf8e9d6 Start working on the F4 PLL 2021-07-29 18:43:13 -03:00
Timo Kröger
895781d0d1 stm32l4: Fix examples crate name 2021-07-29 18:14:01 +02:00
Timo Kröger
9342497132 stm32wl55: Use Dbgmcu::enable_all 2021-07-29 17:38:40 +02:00
Timo Kröger
cad43587e6 stm32l0: Use embassy::main for examples 2021-07-29 17:37:32 +02:00
Dario Nieuwenhuis
1ed65cb9e0
Merge pull request #328 from embassy-rs/remove_peripehral_shared 
Remove embassy_hal_common::peripheral_shared
 2021-07-29 17:22:25 +02:00
Timo Kröger
4ccac69929 stm32l4: Cleanup examples 
* Use `cortex_m_rt::entry` for sync examples
* Use `Dbgmcu::enable_all()` everywhere
 2021-07-29 15:54:11 +02:00
Timo Kröger
2a4890165d stm32f0: Enable debug access in low power modes 2021-07-29 15:35:23 +02:00
Dario Nieuwenhuis
e13774574f Remove embassy_hal_common::peripheral_shared 2021-07-29 14:10:17 +02:00
Dario Nieuwenhuis
01e0a3928f
Merge pull request #326 from embassy-rs/extras-rename 
Rename embassy-extras to embassy-hal-common
 2021-07-29 13:53:03 +02:00
Dario Nieuwenhuis
1457ade49b
Merge pull request #325 from embassy-rs/update-chiptool 
Update chiptool
 2021-07-29 13:47:37 +02:00
Dario Nieuwenhuis
7bfb763e09 Rename embassy-extras to embassy-hal-common 2021-07-29 13:44:51 +02:00
Dario Nieuwenhuis
8d76c582f5 Update chiptool 2021-07-29 13:39:19 +02:00
Dario Nieuwenhuis
c8a48d726a
Merge pull request #277 from Liamolucko/fix-peripheral-ub 
extras: Fix UB in `Peripheral`
 2021-07-29 13:08:30 +02:00
Liam Murphy
cd1a3fcff3 Don't bother supporting creating a PeripheralMutex in an exception handler 2021-07-29 15:19:57 +10:00
Liam Murphy
d5ba35424d Replace PeripheralStateUnchecked with register_interrupt_unchecked 2021-07-29 15:11:26 +10:00
Bob McWhirter
61340d8c65
Merge pull request #320 from bobmcwhirter/data-update-28jul 
Align with -data HEAD.
 2021-07-28 15:45:29 -04:00
Bob McWhirter
d3d74fecdb Align with -data HEAD. 2021-07-28 15:21:39 -04:00
Bob McWhirter
6e4f4b63a8
Merge pull request #317 from bobmcwhirter/peri_irq 
Peri irq
 2021-07-28 15:16:51 -04:00
Bob McWhirter
d8c6ffe3a2 Revert "Optimize CI" 
This reverts commit fe58e9541d.
 2021-07-28 09:24:45 -04:00
Bob McWhirter
abe13e6b18 Trivial to trigger checks from CI. 2021-07-28 09:09:19 -04:00
Liam Murphy
4d9514cbcb Don't allow disabling interrupts wrapped by PeripheralMutex 2021-07-28 21:39:31 +10:00
Liam Murphy
68c93256bc fix: interrupts with equal priority can't preempt each other 2021-07-28 21:31:31 +10:00
Dario Nieuwenhuis
126407f8c8
Merge pull request #319 from timokroeger/stm32f4-embassymain 
Use `embassy::main` macro for stm32f4 examples
 2021-07-28 10:34:46 +02:00
Bob McWhirter
ee755a729f Update to new stm32-data with better multicore NVIC parsing. 2021-07-27 13:49:14 -04:00
Bob McWhirter
8759213fcc Use new interrupt! table format to /enable/ the IRQs also. 2021-07-27 13:23:33 -04:00
Bob McWhirter
b910551c9a Generate more rows in the interrupts! table. 
Adjust DMA/BDMA to use the new style.
 2021-07-27 12:52:01 -04:00
Bob McWhirter
9fec792a6a Update data to include peripheral IRQs. 2021-07-27 12:39:34 -04:00
Timo Kröger
dd1ec8ebec Use embassy::main macro for stm32f4 examples 2021-07-27 15:03:18 +02:00
Liam Murphy
a6fea3cb28 Fix #[cfg]s in exception_to_system_handler 2021-07-27 17:40:13 +10:00
Liam Murphy
e57ca5f7db Remove critical-section dependency 2021-07-27 17:30:10 +10:00
Liam Murphy
079526559f Remove critical sections from PeripheralMutex interrupt handler by checking the interrupt's priority on startup. 
Since `PeripheralMutex` is the only way to safely maintain state across interrupts, and it no longer allows setting the interrupt's priority, the priority changing isn't a concern.

This also prevents other causes of UB due to the interrupt being exposed during `with`, and allowing enabling the interrupt and setting its context to a bogus pointer.
 2021-07-27 17:28:52 +10:00
Thales
d83cd3fffd
Merge pull request #315 from embassy-rs/ci-fixes 
Optimize CI
 2021-07-26 19:24:54 -03:00
Bob McWhirter
754b5ebefc
Merge pull request #316 from bobmcwhirter/update-stm32data 
PR to test change to stm32-data.
 2021-07-26 16:18:06 -04:00
Bob McWhirter
1a3fd765ad Update stm32-data. 2021-07-26 16:12:41 -04:00
Dario Nieuwenhuis
fe58e9541d Optimize CI 2021-07-24 15:29:31 +02:00
Dario Nieuwenhuis
495d977b03
Merge pull request #314 from embassy-rs/example-cleanup-l4 
stm32/examples: cleanup L4
 2021-07-24 14:03:42 +02:00
Dario Nieuwenhuis
5b0ae5c25b stm32/examples: cleanup L4 2021-07-24 13:57:11 +02:00
Dario Nieuwenhuis
4899168534
Merge pull request #312 from timokroeger/en-exti-clock 
Enable SYSCFG clock in `exti::init()`
 2021-07-24 11:18:46 +02:00
Timo Kröger
06fb2a7a80 Enable SYSCFG clock in exti::init() 2021-07-24 11:13:49 +02:00