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562 Commits

Author SHA1 Message Date
Matous Hybl
a1f7a94c69 Add low level timer API. 2022-01-13 16:05:54 +01:00
Ulf Lilleengen
2bc105803a Make exti an optional feature 
* Add embassy-stm32 build with exti
* Add exti to examples
 2022-01-12 14:28:10 +01:00
Dario Nieuwenhuis
3486d59d73 stm32: remove Dbgmcu from public API. 
The use case is already covered by `config.enable_debug_during_sleep`.
 2022-01-05 00:00:44 +01:00
Dario Nieuwenhuis
2eb0cc5df7 stm32/rcc: remove Rcc struct, RccExt trait. 
All the RCC configuration is executed in init().
 2022-01-05 00:00:44 +01:00
Dario Nieuwenhuis
c3fd9a0f44 stm32/rcc: f4/f7 cleanup and make a bit more consistent. 2022-01-04 21:17:17 +01:00
Dario Nieuwenhuis
b06e705a73 stm32/rcc: change family-specific code from dirs to single files. 
Consistent with how other peripherals handle their versions.
 2022-01-04 19:28:15 +01:00
Dario Nieuwenhuis
89b009b11d stm32h7/rcc: remove unneeded DMA enable settings. 
These are automatically enabled by dma::init().
 2022-01-04 13:31:30 +01:00
Dario Nieuwenhuis
5d2f40b337 stm32wl/rcc: remove unneded gpio enables in RCC. 
These are already done by gpio::init().
 2022-01-04 13:31:30 +01:00
Dario Nieuwenhuis
cdc66e110f stm32/rcc: remove builders on Config. 
This makes API consistent with other Config structs in Embassy, where
the convention is to not use builders.
 2022-01-04 13:31:30 +01:00
bors[bot]
cdfd128185
Merge #545 
545: Add adapter for implementing async traits for blocking types r=lulf a=lulf

This allows writing drivers relying on async traits, while still
functioning with implementations that already implement the embedded-hal
traits.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
 2022-01-03 14:17:21 +00:00
bors[bot]
c0e94a7042
Merge #563 
563: Initial ADC support for on STM32F1xx  r=Dirbaio a=sjoerdsimons

Add an ADC implementation for F1 based chips. Primarily tested using ADC1, proper functionality for ADC2 probably needs some extra work as it's mainly a slave and can't e.g. measure vrefint by itself.

Needs https://github.com/embassy-rs/stm32-data/pull/115

Co-authored-by: Sjoerd Simons <sjoerd@collabora.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
 2022-01-01 11:45:23 +00:00
bors[bot]
c20ef419a6
Merge #558 
558: Port buffered uart to v1 stm32 hardware r=Dirbaio a=DCNick3

#526 seems to suggest that it will be rewritten for DMA support, but I am not sure how to implement it and the port was quite straightforward, so here it is. It might be immediately useful before DMA version will be implemented

Note that I have not tested this on v2 hardware

Co-authored-by: Nikita Strygin <nikita6@bk.ru>
 2022-01-01 10:51:14 +00:00
Sjoerd Simons
92f2c6d09c adc: Implement support for f1 ADC block 
Add basic support for the STM32F1xx ADC blocks.
 2021-12-30 10:51:54 +01:00
Sjoerd Simons
a93b1141e9 stm32f1: Store adc clock rate in Clocks struct 2021-12-30 10:50:28 +01:00
Ben Gamari
8da6471a50 stm32/dac: Fix disable_channel 
Previously disable_channel enabled rather than disabled the requested
channel due to an apparent copy-paste error. Refactor to eliminate this
sort of issue by construction.
 2021-12-28 23:27:59 -05:00
Nikita Strygin
a94932be02 Mark clear_interrupt_flag as unsafe 2021-12-26 18:29:41 +03:00
Nikita Strygin
6b08c70273 Port buffered uart to v1 stm32 hardware 
- No DMA
- Create clear_interrupt_flag function to
    handle differences between v1 and v2 hardware
 2021-12-26 18:13:19 +03:00
Dario Nieuwenhuis
d1740b10f0 Lower some verbose logs to trace. 2021-12-23 13:43:14 +01:00
Ulf Lilleengen
3811c0a401 Add adapter for implementing async traits for blocking types 
This allows writing drivers relying on async traits, while still
functioning with implementations that already implement the embedded-hal
traits.

Add examples to stm32l4 for using this feature.
 2021-12-17 12:54:51 +01:00
Ulf Lilleengen
2bbd1ddb8a Remove unneeded rustfmt::skip 2021-12-16 11:37:53 +01:00
Ulf Lilleengen
985c11fad5 Update rust-toolchain 2021-12-16 11:34:20 +01:00
bors[bot]
d5a3064c2c
Merge #540 
540: Initial support for STM32F3 r=Dirbaio a=VasanthakumarV

The [companion PR](https://github.com/embassy-rs/stm32-data/pull/109) in `stm32-data` should be merged before this PR.
The examples were tested on an STM32F303VC MCU.

Co-authored-by: VasanthakumarV <vasanth260m12@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
 2021-12-16 07:30:03 +00:00
Grant Miller
6597e67036 Add finish_dma function 2021-12-14 17:46:25 -06:00
Grant Miller
a13a7a6616 Replace wait_for_idle with spin_until_idle 2021-12-14 17:46:25 -06:00
Grant Miller
e75cb1a564 Regs type alias 2021-12-14 15:39:00 -06:00
Grant Miller
b06658c195 Refactor new 2021-12-14 15:39:00 -06:00
VasanthakumarV
78c5d65ca9 [lint] Add newline in pwr file 2021-12-13 18:16:58 +05:30
VasanthakumarV
3f33d307ff [feature] Add rcc register support for F3 2021-12-13 14:50:13 +05:30
VasanthakumarV
e2c074d133 [feature] Add pwr register support for F3 2021-12-13 13:49:41 +05:30
huntc
45ef944457 Stm flush required implementing also, along with std alloc split 2021-12-10 15:11:41 +11:00
Matous Hybl
1dd5a71c07 Add DCMI peripheral support. 2021-12-09 12:56:39 +01:00
Dario Nieuwenhuis
4ddd23d623 stm32/usart: unify v1 and v2 2021-12-08 05:12:48 +01:00
Dario Nieuwenhuis
022c4cb739 stm32/dma: simplify impls a bit. 2021-12-08 03:30:07 +01:00
Dario Nieuwenhuis
b316d2620c stm32/dma: improve trait docs, seal Word. 2021-12-08 03:18:15 +01:00
Dario Nieuwenhuis
6179da6b9c stm32/dma: eagerly start transfers when calling the functions. 
`async fn`s do nothing until polled, but we want the DMA transfer to
immediately start in this case. Drivers rely on it. Some require special
orders, such as "start DMA, start SPI, then wait for DMA" which is awkward
to do without eager start.

Also use a manually-impl'd future, this allows getting rid of the "double"
Unborrow channel clone.
 2021-12-08 03:04:39 +01:00
Dario Nieuwenhuis
4e349d0f5d stm32/dma: use the right waker slot number for DMA2 (must add 8) 2021-12-08 01:54:31 +01:00
Dario Nieuwenhuis
fd2fe62b5f stm32/dma: rename is_stopped to is_running. 
Note that this does NOT invert the result of `en()` because it was
wrong before.
 2021-12-08 01:51:39 +01:00
Matous Hybl
b2910558d3 Refactor DMA traits. 2021-12-07 21:43:47 +01:00
Joshua Salzedo
e2719aba10 Further extend the dma channel trait 2021-12-07 21:43:47 +01:00
Joshua Salzedo
93e047ede2 cargo fmt 2021-12-07 21:43:47 +01:00
Joshua Salzedo
3411039cb9 Implement extended Channel trait to bdma.rs 2021-12-07 21:43:47 +01:00
Joshua Salzedo
2d2c6d0e01 Implement extended Channel trait to dma.rs 2021-12-07 21:43:47 +01:00
Joshua Salzedo
3272987d92 Expand channel trait 2021-12-07 21:43:47 +01:00
Ulf Lilleengen
f9ac0c8047 Add back MISO flush 2021-12-07 09:40:45 +01:00
Grant Miller
79baa04118 Implement blocking traits with a macro 2021-12-07 00:03:52 -06:00
Grant Miller
bf1f80afa1 Unify blocking trait impls 2021-12-07 00:03:52 -06:00
Grant Miller
3a17e3a2a5 Move async trait impls to mod 2021-12-07 00:03:52 -06:00
Grant Miller
20d2151b1d check_error_flags function 2021-12-07 00:03:52 -06:00
Grant Miller
496579b48b Move Word trait to mod 2021-12-07 00:03:52 -06:00
Grant Miller
7c78247be3 v2: set frxth and ds in new 2021-12-06 22:36:53 -06:00
Grant Miller
d76bc45e30 Move Spi drop impl to mod 2021-12-06 17:19:55 -06:00
Grant Miller
bd9e730024 Move set_word_size to mod 2021-12-06 16:47:08 -06:00
Grant Miller
a35b7d90bc Add tx_ptr and rx_ptr methods 2021-12-06 16:33:06 -06:00
Grant Miller
a35f337bd6 Move Spi::new and Spi::compute_baud_rate to mod 2021-12-06 15:19:24 -06:00
Grant Miller
75374ce7e8 Fix ssoe in v1 2021-12-06 14:57:53 -06:00
Grant Miller
e1cccc8391 Move Spi to mod (without NoDma defaults) 2021-12-06 14:47:50 -06:00
Grant Miller
aeb69a7665 Track current word size in v2 and v3 also 2021-12-06 14:24:02 -06:00
Grant Miller
d51885c0eb Move WordSize methods to mod 2021-12-06 14:13:25 -06:00
Grant Miller
d426caefbf Move NoPin impls from v1 to mod 2021-12-06 14:02:21 -06:00
Ulf Lilleengen
81ec4c82fd Flush MISO before transfer operation 2021-12-03 09:53:28 +01:00
Matous Hybl
6e0eb33ea8 Downcast timer to GP16 for time drivers. 2021-12-02 18:07:05 +01:00
Matous Hybl
f0cb77443c Fix wrong pin configuration in STM32's SPI v3. 2021-12-01 22:18:14 +01:00
Dario Nieuwenhuis
b0fabfab5d Update stm32-data: rcc regs info comes from yamls now. 2021-11-29 02:28:02 +01:00
Ulf Lilleengen
25b49a8a2a Remove common clock types 
Different STM32 RCC peripherals have different capabilities and register
values. Define types for each RCC types inside each module to ensure
full range of capabilities for each family can be used
 2021-11-28 16:46:08 +01:00
Dario Nieuwenhuis
006e567716 stm32/pwm: allow using the advanced timer instances too. 2021-11-27 03:06:53 +01:00
Dario Nieuwenhuis
d7d1258411 stm32/pwm: small cleanups 2021-11-27 03:05:10 +01:00
Dario Nieuwenhuis
22fad1e7bc stm32/pwm: impl instance/pin for all chips 2021-11-27 03:04:50 +01:00
Ben Gamari
8211d58ee2 stm32/pwm: initial commit 2021-11-27 02:50:30 +01:00
Dario Nieuwenhuis
88d4b0c00d stm32: add stm32g4 support. 2021-11-27 02:34:23 +01:00
Ulf Lilleengen
cd9a1d547c Ensure SPI DMA write is completed 
Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.
 2021-11-24 14:59:18 +01:00
Wilfried Chauveau
eac604accd
Fix missing lifetime bounds 2021-11-21 10:10:28 +00:00
Dario Nieuwenhuis
24e5013c00 Allow unused to fix build failure in u5 2021-11-17 21:43:05 +01:00
Bob McWhirter
c2da498263 Update to defmt 3.0ish. 
Lots of gitrevs deps.
 2021-11-15 11:09:08 -05:00
bors[bot]
8193885cb5
Merge #482 
482: Add MCO peripheral. r=Dirbaio a=matoushybl

This PR adds an abstraction over STM32 RCC feature called MCO (Microcontroller Clock Output). The clock output can bind to several clock sources and then can be scaled using a prescaler.

Given that from the embassy ecosystem the RCC is generaly invisible to the user, the MCO was implemented as a separate peripheral bound to the pin where the clock should appear.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
 2021-11-11 16:20:02 +00:00
Matous Hybl
c14642cffc Add MCO peripheral. 2021-11-11 11:34:09 +01:00
bors[bot]
96e2f0dfc5
Merge #468 
468: Add v1c ethernet driver for the STM32F7 family. r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
 2021-11-10 22:07:38 +00:00
Matous Hybl
f0ba79059e Add v1c ethernet driver for the STM32F7 family. 2021-11-10 10:16:46 +01:00
Bob McWhirter
12a64b867b More support for U5 PWR (ish), RCC, and FLASH (ish). 2021-11-08 14:27:33 -05:00
Bob McWhirter
5f124ec49f Update U5 to init RCC. 2021-11-08 14:20:51 -05:00
Matous Hybl
9b5d9fbfca Fix v2 ethernet pin definitions. Fix ethernet example for H7 nucleos. 2021-11-04 16:25:30 +01:00
Bob McWhirter
d1272e00bb Prefix unused variable for now. 2021-11-02 15:45:56 -04:00
Bob McWhirter
44056c2e75 Less allowy. 2021-11-02 15:32:20 -04:00
Bob McWhirter
076c795ebb Even more allowed unused. 2021-11-02 15:28:14 -04:00
Bob McWhirter
6bbf450478 Allow unused macros temporarily until U5 supports DMA. 2021-11-02 15:20:42 -04:00
Bob McWhirter
705523d0ea Fix formatting. 2021-11-02 12:13:42 -04:00
Bob McWhirter
f12b70535b Adjust for STM32U5. 2021-11-02 12:05:24 -04:00
Bob McWhirter
bbff98ed0d Move the use inside the macro call, inside another set of braces in case it percolates up twice. 2021-10-26 14:34:03 -04:00
Bob McWhirter
a72816492a Only attempt to enable the dmamux peri clock if it has an enable bit. 2021-10-26 14:19:03 -04:00
Bob McWhirter
959aecf6ac Enable the DMAMUX clocks. 2021-10-26 14:01:39 -04:00
Matous Hybl
015cad84dd Initial support for STM32F767ZI. 2021-10-26 17:33:28 +02:00
bors[bot]
01e5376b25
Merge #456 
456: Fix L4 clock setup for MSI and PLL to allow RNG operation r=Dirbaio a=lulf

Example is tested on STM32L475VG.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
 2021-10-26 11:59:14 +00:00
Ulf Lilleengen
e55726964d Fix clock setup for MSI and PLL to allow RNG opereation 
Add RNG example using PLL as clock source.
 2021-10-26 13:45:53 +02:00
Ulf Lilleengen
f8ebc967a9 Add implementation of async trait for STM32 I2C v2 
* Add DMA read implementation for I2C v2
* Add example using DMA for I2C
 2021-10-21 12:30:02 +02:00
Ulf Lilleengen
d2a79a46c5 Configure the correct pin instances 2021-10-21 11:57:00 +02:00
Tobias Pisani
43a7226d8b inline FRE register check for SPI on F1 2021-10-11 23:33:32 +02:00
Tobias Pisani
2cbb8a7ece Add AFType::Input for input configurations. 2021-10-11 22:57:21 +02:00
Tobias Pisani
259e84e68e Make miso/mosi optional when for unidirectional spi 
Only suported on v1 currently
 2021-10-11 22:57:21 +02:00
Tobias Pisani
c44bed300b Correctly set alternate function for stm32f1 gpios 2021-10-11 22:57:21 +02:00
Tobias Pisani
091e7e1f98 Generate USART pin definitions for stm32f1 2021-10-11 22:57:21 +02:00
Tobias Pisani
39880de958 partial alternate function configuration on STM32f1 2021-10-11 22:57:10 +02:00