Commit Graph

159 Commits

Author SHA1 Message Date
1fdce6e52a Merge #1360 #1361
1360: stm32/rcc: add i2s pll on some f4 micros r=Dirbaio a=xoviat

Adds the i2s pll on some f4 micros. 

1361: Executor: Replace unnecessary atomics in runqueue r=Dirbaio a=GrantM11235

Only the head pointer needs to be atomic. The `RunQueueItem` pointers are only loaded and stored, and never concurrently

Co-authored-by: xoviat <xoviat@users.noreply.github.com>
Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2023-04-15 10:38:28 +00:00
f395ec44e8 stm32/rcc: add pllsai clock 2023-04-14 21:28:27 -05:00
650589ab3f stm32/rcc: add plli2s to Clocks and cfg directives 2023-04-14 16:30:36 -05:00
c1d5f86871 stm32/rcc: fix warnings 2023-04-12 18:11:55 -05:00
0289630fe4 stm32/rcc: add i2s pll on some f4 micros 2023-04-12 18:04:44 -05:00
f3699e67b9 Fix typo in derivation of PLLP divisor 2023-04-12 02:07:31 +02:00
611d023829 stm32: add H5 support. 2023-04-06 18:59:37 +02:00
1349dabe1a add compilation time exclusion for stm32f410 2023-04-03 17:55:05 +02:00
4ce1c5f27d Add MCO support for L4 and F4 families 2023-04-03 16:41:25 +02:00
13f0c64a8c Fix APB clock calculation for several STM32 families 2023-03-16 21:21:39 -06:00
d21643c060 fix "prescaler none" which incorrectly set "prescaler divided by 3" 2023-02-12 11:36:57 +01:00
5e3c33b777 Fix rcc prescaler for wb55 HCLK1
- fix prescaler not divided which incorrectly set prescaler divided by 3
2023-01-21 14:39:25 +01:00
f604153f05 stm32/rcc: print actual freqs on boot. 2023-01-20 16:31:04 +01:00
2a349afea7 stm32: add stm32c0 support. 2023-01-17 21:28:16 +01:00
041531c829 stm32/rcc: fix u5 pll, add hsi48. 2023-01-11 17:57:22 +01:00
84240d49ea stm32wl: Fix RCC
* `MSIRGSEL = 1` was required for MSI accept the updated MSI range
* Reorder enable and clock switching to properly handle the jump from
the default 4MHz MSI to a higher MSI freuquency
2022-08-26 15:44:58 +02:00
2649f13dc7 stm32/rcc: fix unnecessary parentheses 2022-08-17 15:03:23 +02:00
4901c34d9c Rename Unborrowed -> PeripheralRef, Unborrow -> Peripheral 2022-07-23 14:00:19 +02:00
5ecbe5c918 embassy-stm32: Simplify time
- Remove unused `MilliSeconds`, `MicroSeconds`, and `NanoSeconds` types
- Remove `Bps`, `KiloHertz`, and `MegaHertz` types that were only used
for converting to `Hertz`
- Replace all instances of `impl Into<Hertz>` with `Hertz`
- Add `hz`, `khz`, and `mhz` methods to `Hertz`, as well as
free function shortcuts
- Remove `U32Ext` extension trait
2022-07-10 21:46:45 -05:00
5a208d28d0 Fix g0 rcc build 2022-07-11 00:37:00 +03:00
3bf1e1d4aa Fix f2, wl compilation 2022-07-10 21:46:14 +03:00
85054a7233 Fix typo 2022-07-10 21:15:38 +03:00
1fd5022e72 Refactor IWDG to use LSI frequency from RCC 2022-07-10 20:59:36 +03:00
397722c328 stm32: fix f100 build. 2022-06-26 23:52:38 +02:00
88e36a70bd Update to 2021 edition. (#820) 2022-06-18 02:15:48 +02:00
a8703b7598 Run rustfmt. 2022-06-12 22:22:31 +02:00
5085100df2 Add embassy-cortex-m crate.
- Move Interrupt and InterruptExecutor from `embassy` to `embassy-cortex-m`.
- Move Unborrow from `embassy` to `embassy-hal-common` (nothing in `embassy` requires it anymore)
- Move PeripheralMutex from `embassy-hal-common` to `embassy-cortex-m`.
2022-06-12 21:45:38 +02:00
1c2b27dcad embassy-stm32: g0: add PLL clock source
STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at
16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach
64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks
its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q`
to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main
    reason the user will configure the PLL, so `r` is mandatory and
	the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S
    peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the
    MCO and MCO2 peripherals, so `q` is optional and the output is
	conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()`
calls `PllConfig::init()` which initializes the PLL per [RM0454]. It
disables the PLL, waits for it to stop, enables the source
oscillator, configures the PLL, waits for it to lock, and then
enables the appropriate outputs. `rcc::init()` then switches the
clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash
wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz
requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This
was likely a blocker for anyone using HSE >= 24 MHz, with or without
the PLL.) Flash accesses are now automatically slowed down as needed
before changing the clock source, and sped up as permitted after
changing the clock source. The number of flash wait states also
determines if flash prefetching will be profitable, so that is now
handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
2022-05-27 23:56:42 -05:00
c90968bb70 stm32/rcc: Modify only relevant CFGR bits and keep the settings previously done.
PLL settings remained intact because these bits are not writable when PLL is enabled,
but prescaler settings were overwritten by selecting PLL as sysclk (CFGR.SW[1:0]).
2022-05-12 09:09:39 +02:00
1a216958ac stm32/rcc: Set flash prefetch buffer and half cycle access according to AHB clock prescaler 2022-05-12 09:09:39 +02:00
01fb447e9d Allow maximal clock for F7 HCLK 2022-05-08 23:07:28 +02:00
96d0eb9476 stm32: Fix stm32f107 build. 2022-05-08 21:37:37 +02:00
e88559c5ca Use defmt-friendly error handling 2022-04-30 11:41:17 +03:00
07ad52162b Add PLL config support for F2 2022-04-29 18:21:40 +03:00
0cfe1dc9df Move HSE config out of main clock mux
This makes the configuration more flexible and closer to the underlying
configuration register structure. For example, we could use HSI for the
system clock, but use HSE to output a clock with MCO.
2022-04-29 17:51:18 +03:00
484e0acc63 Add stm32 flash + bootloader support
* Add flash drivers for L0, L1, L4, WB and WL. Not tested for WB, but
should be similar to WL.
* Add embassy-boot-stm32 for bootloading on STM32.
* Add flash examples and bootloader examples
* Update stm32-data
2022-04-27 15:17:18 +02:00
6d0e6d563d Merge #714
714: add more clock options for l4 and l5 r=Dirbaio a=ant32

- added an assert so it panics if pll48div is not 48Mhz
- added MSI as a clock source for PLL
- removed hsi48 option for MCUs mentioned in l4 rcc presentation
- copied some code from l4 to l5, but don't have a way of testing it.

Co-authored-by: Philip A Reimer <antreimer@gmail.com>
2022-04-12 21:42:36 +00:00
371f3ef419 Add ADC support for H7 2022-04-12 22:25:00 +02:00
d90ecbbe40 add more clock options for l4 and l5 2022-04-11 19:11:02 -06:00
d8860c0b80 add stm32l4 hsi48 and usb example 2022-04-09 14:55:03 -06:00
8b757e1aec Add stm32wlexx support 2022-04-08 03:43:58 +02:00
50ff63ab88 Add STM32L5 support. 2022-04-08 03:11:38 +02:00
1f59f8e7d0 add pllsai1 and allow for 120Mhz clock on stm32l4+ 2022-04-01 22:42:43 -06:00
a608d0deaf Add minimal STM32F2 RCC
No support for PLL or other clocks than SYSCLK/AHB/APB1/APB2
2022-03-27 18:40:49 +03:00
609975f821 rustfmt 2022-03-04 18:04:12 +01:00
047ff9a2f2 Use new stm32-data registers and fix AHB clock calculation
The original code for calculating the AHB clock did not account for the gap in
prescaler values (32 is not an available value.) The bit shifting and math has
been replaced by a `match`.
2022-03-04 18:03:55 +01:00
ea5cd19c30 stm32: fix build for h7ab 2022-02-24 06:28:29 +01:00
e8ca5f9b04 stm32/rcc: fix build on l0 chips without CRS 2022-02-24 06:28:29 +01:00
30ce71127a stm32: move MCO pin impls to build.rs 2022-02-23 19:54:46 +01:00
1e69a8c484 stm32: move pin trait impls from macrotables to build.rs 2022-02-23 19:54:46 +01:00