stm32/build: deterministically generate data

stm32: fix low-power test

ci.sh

@@ -192,9 +192,13 @@ cargo batch  \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g071rb --out-dir out/tests/stm32g071rb \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c031c6 --out-dir out/tests/stm32c031c6 \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi --out-dir out/tests/stm32h755zi \
+    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h753zi --out-dir out/tests/stm32h753zi \
+    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7a3zi --out-dir out/tests/stm32h7a3zi \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb55rg --out-dir out/tests/stm32wb55rg \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h563zi --out-dir out/tests/stm32h563zi \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u585ai --out-dir out/tests/stm32u585ai \
+    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u5a5zj --out-dir out/tests/stm32u5a5zj \
+    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wba52cg --out-dir out/tests/stm32wba52cg \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l073rz --out-dir out/tests/stm32l073rz \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32l152re --out-dir out/tests/stm32l152re \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l4a6zg --out-dir out/tests/stm32l4a6zg \
@@ -204,6 +208,7 @@ cargo batch  \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f207zg --out-dir out/tests/stm32f207zg \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f303ze --out-dir out/tests/stm32f303ze \
     --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l496zg --out-dir out/tests/stm32l496zg \
+    --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wl55jc --out-dir out/tests/stm32wl55jc \
     --- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/rpi-pico \
     --- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \
     --- build --release --manifest-path tests/riscv32/Cargo.toml --target riscv32imac-unknown-none-elf \
@@ -212,8 +217,13 @@ cargo batch  \
 
 rm out/tests/stm32wb55rg/wpan_mac
 rm out/tests/stm32wb55rg/wpan_ble
+
+# unstable, I think it's running out of RAM?
 rm out/tests/stm32f207zg/eth
 
+# doesn't work, gives "noise error", no idea why. usart_dma does pass.
+rm out/tests/stm32u5a5zj/usart
+
 if [[ -z "${TELEPROBE_TOKEN-}" ]]; then
     echo No teleprobe token found, skipping running HIL tests
     exit

cyw43/src/control.rs

@@ -1,7 +1,7 @@
 use core::cmp::{max, min};
 
-use ch::driver::LinkState;
 use embassy_net_driver_channel as ch;
+use embassy_net_driver_channel::driver::{HardwareAddress, LinkState};
 use embassy_time::Timer;
 
 pub use crate::bus::SpiBusCyw43;
@@ -133,7 +133,7 @@ impl<'a> Control<'a> {
 
         Timer::after_millis(100).await;
 
-        self.state_ch.set_ethernet_address(mac_addr);
+        self.state_ch.set_hardware_address(HardwareAddress::Ethernet(mac_addr));
 
         debug!("INIT DONE");
     }

docs/modules/ROOT/pages/basic_application.adoc

@@ -48,7 +48,7 @@ The `Spawner` is the way the main application spawns other tasks. The `Periphera
 include::example$basic/src/main.rs[lines="22..-1"]
 ----
 
-What happens when the `blinker` task has been spawned and main returns? Well, the main entry point is actually just like any other task, except that you can only have one and it takes some specific type arguments. The magic lies within the `#[embassy::main]` macro. The macro does the following:
+What happens when the `blinker` task has been spawned and main returns? Well, the main entry point is actually just like any other task, except that you can only have one and it takes some specific type arguments. The magic lies within the `#[embassy_executor::main]` macro. The macro does the following:
 
 . Creates an Embassy Executor
 . Initializes the microcontroller HAL to get the `Peripherals`

embassy-net-driver-channel/CHANGELOG.md

@@ -5,14 +5,12 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## 0.2.0 - 2023-10-15
+## 0.2.0 - 2023-10-18
 
-- Update embassy-net-driver
-- `Runner::new` now takes an `embassy_net_driver::HardwareAddress` parameter
-- Added `Runner::set_ieee802154_address`, `Runner::ieee802154_address`
+- Update `embassy-net-driver` to v0.2
+- `Runner::new` now takes an `embassy_net_driver::HardwareAddress` parameter.
+- `Runner::set_ethernet_address` is now `set_hardware_address`.
 
 ## 0.1.0 - 2023-06-29
 
 - First release
-
-

embassy-net-driver-channel/README.md

@@ -7,7 +7,9 @@ The `embassy-net-driver` trait is polling-based. To implement it, you must write
 hand, and hook up the `Waker`s provided by `embassy-net` to the right interrupt handlers so that `embassy-net`
 knows when to poll your driver again to make more progress.
 
-With `embassy-net-driver-channel`
+With `embassy-net-driver-channel` you get a "channel-like" interface instead, where you can send/receive packets
+to/from embassy-net. The intended usage is to spawn a "driver task" in the background that does this, passing
+packets between the hardware and the channel.
 
 ## A note about deadlocks
 
@@ -18,19 +20,19 @@ loop {
     // Wait for either..
     match select(
         // ... the chip signaling an interrupt, indicating a packet is available to receive, or
-        irq_pin.wait_for_low(), 
+        irq_pin.wait_for_low(),
         // ... a TX buffer becoming available, i.e. embassy-net wants to send a packet
         tx_chan.tx_buf(),
     ).await {
         Either::First(_) => {
             // a packet is ready to be received!
             let buf = rx_chan.rx_buf().await; // allocate a rx buf from the packet queue
-            let n = receive_packet_over_spi(buf).await; 
+            let n = receive_packet_over_spi(buf).await;
             rx_chan.rx_done(n);
         }
         Either::Second(buf) => {
             // a packet is ready to be sent!
-            send_packet_over_spi(buf).await; 
+            send_packet_over_spi(buf).await;
             tx_chan.tx_done();
         }
     }
@@ -41,7 +43,7 @@ However, this code has a latent deadlock bug. The symptom is it can hang at `rx_
 
 The reason is that, under load, both the TX and RX queues can get full at the same time. When this happens, the `embassy-net` task stalls trying to send because the TX queue is full, therefore it stops processing packets in the RX queue. Your driver task also stalls because the RX queue is full, therefore it stops processing packets in the TX queue.
 
-The fix is to make sure to always service the TX queue while you're waiting for space to become available in the TX queue. For example, select on either "tx_chan.tx_buf() available" or "INT is low AND rx_chan.rx_buf() available":
+The fix is to make sure to always service the TX queue while you're waiting for space to become available in the RX queue. For example, select on either "tx_chan.tx_buf() available" or "INT is low AND rx_chan.rx_buf() available":
 
 ```rust,ignore
 loop {
@@ -58,12 +60,12 @@ loop {
     ).await {
         Either::First(buf) => {
             // a packet is ready to be received!
-            let n = receive_packet_over_spi(buf).await; 
+            let n = receive_packet_over_spi(buf).await;
             rx_chan.rx_done(n);
         }
         Either::Second(buf) => {
             // a packet is ready to be sent!
-            send_packet_over_spi(buf).await; 
+            send_packet_over_spi(buf).await;
             tx_chan.tx_done();
         }
     }
@@ -79,12 +81,10 @@ These `embassy-net` drivers are implemented using this crate. You can look at th
 - [`embassy-net-wiznet`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-wiznet) for Wiznet SPI Ethernet MAC+PHY chips.
 - [`embassy-net-esp-hosted`](https://github.com/embassy-rs/embassy/tree/main/embassy-net-esp-hosted) for using ESP32 chips with the [`esp-hosted`](https://github.com/espressif/esp-hosted) firmware as WiFi adapters for another non-ESP32 MCU.
 
-
 ## Interoperability
 
 This crate can run on any executor.
 
-
 ## License
 
 This work is licensed under either of

embassy-net-driver-channel/src/lib.rs

@@ -8,9 +8,8 @@ use core::cell::RefCell;
 use core::mem::MaybeUninit;
 use core::task::{Context, Poll};
 
-use driver::HardwareAddress;
 pub use embassy_net_driver as driver;
-use embassy_net_driver::{Capabilities, LinkState, Medium};
+use embassy_net_driver::{Capabilities, LinkState};
 use embassy_sync::blocking_mutex::raw::NoopRawMutex;
 use embassy_sync::blocking_mutex::Mutex;
 use embassy_sync::waitqueue::WakerRegistration;
@@ -161,18 +160,10 @@ impl<'d> StateRunner<'d> {
         });
     }
 
-    pub fn set_ethernet_address(&self, address: [u8; 6]) {
+    pub fn set_hardware_address(&self, address: driver::HardwareAddress) {
         self.shared.lock(|s| {
             let s = &mut *s.borrow_mut();
-            s.hardware_address = driver::HardwareAddress::Ethernet(address);
-            s.waker.wake();
-        });
-    }
-
-    pub fn set_ieee802154_address(&self, address: [u8; 8]) {
-        self.shared.lock(|s| {
-            let s = &mut *s.borrow_mut();
-            s.hardware_address = driver::HardwareAddress::Ieee802154(address);
+            s.hardware_address = address;
             s.waker.wake();
         });
     }
@@ -232,11 +223,6 @@ pub fn new<'d, const MTU: usize, const N_RX: usize, const N_TX: usize>(
 ) -> (Runner<'d, MTU>, Device<'d, MTU>) {
     let mut caps = Capabilities::default();
     caps.max_transmission_unit = MTU;
-    caps.medium = match &hardware_address {
-        HardwareAddress::Ethernet(_) => Medium::Ethernet,
-        HardwareAddress::Ieee802154(_) => Medium::Ieee802154,
-        HardwareAddress::Ip => Medium::Ip,
-    };
 
     // safety: this is a self-referential struct, however:
     // - it can't move while the `'d` borrow is active.

embassy-net-driver/CHANGELOG.md

@@ -5,13 +5,13 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## 0.2.0 - 2023-10-15
+## 0.2.0 - 2023-10-18
 
-- Added `Driver::ieee802154_address`
-- Added `Medium::Ieee802154`
+- Added support for IEEE 802.15.4 mediums.
+- Added `Driver::hardware_address()`, `HardwareAddress`.
+- Removed `Medium` enum. The medium is deduced out of the hardware address.
+- Removed `Driver::ethernet_address()`. Replacement is `hardware_address()`.
 
 ## 0.1.0 - 2023-06-29
 
 - First release
-
-

embassy-net-driver/src/lib.rs

@@ -7,12 +7,23 @@ use core::task::Context;
 /// Representation of an hardware address, such as an Ethernet address or an IEEE802.15.4 address.
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
 pub enum HardwareAddress {
-    /// A six-octet Ethernet address
+    /// Ethernet medium, with a A six-octet Ethernet address.
+    ///
+    /// Devices of this type send and receive Ethernet frames,
+    /// and interfaces using it must do neighbor discovery via ARP or NDISC.
+    ///
+    /// Examples of devices of this type are Ethernet, WiFi (802.11), Linux `tap`, and VPNs in tap (layer 2) mode.
     Ethernet([u8; 6]),
-    /// An eight-octet IEEE802.15.4 address
+    /// 6LoWPAN over IEEE802.15.4, with an eight-octet address.
     Ieee802154([u8; 8]),
-    /// Indicates that a Driver is IP-native, and has no hardware address
+    /// Indicates that a Driver is IP-native, and has no hardware address.
+    ///
+    /// Devices of this type send and receive IP frames, without an
+    /// Ethernet header. MAC addresses are not used, and no neighbor discovery (ARP, NDISC) is done.
+    ///
+    /// Examples of devices of this type are the Linux `tun`, PPP interfaces, VPNs in tun (layer 3) mode.
     Ip,
 }
 
@@ -64,6 +75,10 @@ pub trait Driver {
     fn capabilities(&self) -> Capabilities;
 
     /// Get the device's hardware address.
+    ///
+    /// The returned hardware address also determines the "medium" of this driver. This indicates
+    /// what kind of packet the sent/received bytes are, and determines some behaviors of
+    /// the interface. For example, ARP/NDISC address resolution is only done for Ethernet mediums.
     fn hardware_address(&self) -> HardwareAddress;
 }
 
@@ -124,13 +139,6 @@ pub trait TxToken {
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[non_exhaustive]
 pub struct Capabilities {
-    /// Medium of the device.
-    ///
-    /// This indicates what kind of packet the sent/received bytes are, and determines
-    /// some behaviors of Interface. For example, ARP/NDISC address resolution is only done
-    /// for Ethernet mediums.
-    pub medium: Medium,
-
     /// Maximum transmission unit.
     ///
     /// The network device is unable to send or receive frames larger than the value returned
@@ -161,32 +169,6 @@ pub struct Capabilities {
     pub checksum: ChecksumCapabilities,
 }
 
-/// Type of medium of a device.
-#[derive(Debug, Eq, PartialEq, Copy, Clone)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Medium {
-    /// Ethernet medium. Devices of this type send and receive Ethernet frames,
-    /// and interfaces using it must do neighbor discovery via ARP or NDISC.
-    ///
-    /// Examples of devices of this type are Ethernet, WiFi (802.11), Linux `tap`, and VPNs in tap (layer 2) mode.
-    Ethernet,
-
-    /// IP medium. Devices of this type send and receive IP frames, without an
-    /// Ethernet header. MAC addresses are not used, and no neighbor discovery (ARP, NDISC) is done.
-    ///
-    /// Examples of devices of this type are the Linux `tun`, PPP interfaces, VPNs in tun (layer 3) mode.
-    Ip,
-
-    /// IEEE 802_15_4 medium
-    Ieee802154,
-}
-
-impl Default for Medium {
-    fn default() -> Medium {
-        Medium::Ethernet
-    }
-}
-
 /// A description of checksum behavior for every supported protocol.
 #[derive(Debug, Clone, Default)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]

embassy-net-enc28j60/src/lib.rs

@@ -19,7 +19,7 @@ mod traits;
 use core::cmp;
 use core::convert::TryInto;
 
-use embassy_net_driver::{Capabilities, HardwareAddress, LinkState, Medium};
+use embassy_net_driver::{Capabilities, HardwareAddress, LinkState};
 use embassy_time::Duration;
 use embedded_hal::digital::OutputPin;
 use embedded_hal::spi::{Operation, SpiDevice};
@@ -671,7 +671,6 @@ where
     fn capabilities(&self) -> Capabilities {
         let mut caps = Capabilities::default();
         caps.max_transmission_unit = MTU;
-        caps.medium = Medium::Ethernet;
         caps
     }
 

embassy-net-esp-hosted/src/control.rs

@@ -1,5 +1,5 @@
-use ch::driver::LinkState;
 use embassy_net_driver_channel as ch;
+use embassy_net_driver_channel::driver::{HardwareAddress, LinkState};
 use heapless::String;
 
 use crate::ioctl::Shared;
@@ -77,7 +77,7 @@ impl<'a> Control<'a> {
 
         let mac_addr = self.get_mac_addr().await?;
         debug!("mac addr: {:02x}", mac_addr);
-        self.state_ch.set_ethernet_address(mac_addr);
+        self.state_ch.set_hardware_address(HardwareAddress::Ethernet(mac_addr));
 
         Ok(())
     }

embassy-net-wiznet/src/lib.rs

@@ -1,14 +1,14 @@
-//! [`embassy-net`](https://crates.io/crates/embassy-net) driver for WIZnet ethernet chips.
 #![no_std]
 #![feature(async_fn_in_trait)]
+#![doc = include_str!("../README.md")]
 
 pub mod chip;
 mod device;
 
-use embassy_futures::select::{select, Either};
+use embassy_futures::select::{select3, Either3};
 use embassy_net_driver_channel as ch;
 use embassy_net_driver_channel::driver::LinkState;
-use embassy_time::Timer;
+use embassy_time::{Duration, Ticker, Timer};
 use embedded_hal::digital::OutputPin;
 use embedded_hal_async::digital::Wait;
 use embedded_hal_async::spi::SpiDevice;
@@ -49,32 +49,34 @@ pub struct Runner<'d, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin> {
 impl<'d, C: Chip, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, C, SPI, INT, RST> {
     pub async fn run(mut self) -> ! {
         let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split();
+        let mut tick = Ticker::every(Duration::from_millis(500));
         loop {
-            if self.mac.is_link_up().await {
-                state_chan.set_link_state(LinkState::Up);
-                loop {
-                    match select(
-                        async {
-                            self.int.wait_for_low().await.ok();
-                            rx_chan.rx_buf().await
-                        },
-                        tx_chan.tx_buf(),
-                    )
-                    .await
-                    {
-                        Either::First(p) => {
-                            if let Ok(n) = self.mac.read_frame(p).await {
-                                rx_chan.rx_done(n);
-                            }
-                        }
-                        Either::Second(p) => {
-                            self.mac.write_frame(p).await.ok();
-                            tx_chan.tx_done();
-                        }
+            match select3(
+                async {
+                    self.int.wait_for_low().await.ok();
+                    rx_chan.rx_buf().await
+                },
+                tx_chan.tx_buf(),
+                tick.next(),
+            )
+            .await
+            {
+                Either3::First(p) => {
+                    if let Ok(n) = self.mac.read_frame(p).await {
+                        rx_chan.rx_done(n);
+                    }
+                }
+                Either3::Second(p) => {
+                    self.mac.write_frame(p).await.ok();
+                    tx_chan.tx_done();
+                }
+                Either3::Third(()) => {
+                    if self.mac.is_link_up().await {
+                        state_chan.set_link_state(LinkState::Up);
+                    } else {
+                        state_chan.set_link_state(LinkState::Down);
                     }
                 }
-            } else {
-                state_chan.set_link_state(LinkState::Down);
             }
         }
     }

embassy-net/CHANGELOG.md

@@ -5,7 +5,7 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
-## 0.2.0 - 2023-10-15
+## 0.2.0 - 2023-10-18
 
 - Re-export `smoltcp::wire::IpEndpoint`
 - Add poll functions on UdpSocket
@@ -27,5 +27,3 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## 0.1.0 - 2023-06-29
 
 - First release
-
-

embassy-net/src/device.rs

@@ -1,7 +1,7 @@
 use core::task::Context;
 
-use embassy_net_driver::{Capabilities, Checksum, Driver, Medium, RxToken, TxToken};
-use smoltcp::phy;
+use embassy_net_driver::{Capabilities, Checksum, Driver, RxToken, TxToken};
+use smoltcp::phy::{self, Medium};
 use smoltcp::time::Instant;
 
 pub(crate) struct DriverAdapter<'d, 'c, T>
@@ -11,6 +11,7 @@ where
     // must be Some when actually using this to rx/tx
     pub cx: Option<&'d mut Context<'c>>,
     pub inner: &'d mut T,
+    pub medium: Medium,
 }
 
 impl<'d, 'c, T> phy::Device for DriverAdapter<'d, 'c, T>
@@ -46,19 +47,7 @@ where
 
         smolcaps.max_transmission_unit = caps.max_transmission_unit;
         smolcaps.max_burst_size = caps.max_burst_size;
-        smolcaps.medium = match caps.medium {
-            #[cfg(feature = "medium-ethernet")]
-            Medium::Ethernet => phy::Medium::Ethernet,
-            #[cfg(feature = "medium-ip")]
-            Medium::Ip => phy::Medium::Ip,
-            #[cfg(feature = "medium-ieee802154")]
-            Medium::Ieee802154 => phy::Medium::Ieee802154,
-            #[allow(unreachable_patterns)]
-            _ => panic!(
-                "Unsupported medium {:?}. Make sure to enable it in embassy-net's Cargo features.",
-                caps.medium
-            ),
-        };
+        smolcaps.medium = self.medium;
         smolcaps.checksum.ipv4 = convert(caps.checksum.ipv4);
         smolcaps.checksum.tcp = convert(caps.checksum.tcp);
         smolcaps.checksum.udp = convert(caps.checksum.udp);

embassy-net/src/lib.rs

@@ -33,6 +33,7 @@ use heapless::Vec;
 pub use smoltcp::iface::MulticastError;
 #[allow(unused_imports)]
 use smoltcp::iface::{Interface, SocketHandle, SocketSet, SocketStorage};
+use smoltcp::phy::Medium;
 #[cfg(feature = "dhcpv4")]
 use smoltcp::socket::dhcpv4::{self, RetryConfig};
 #[cfg(feature = "medium-ethernet")]
@@ -264,14 +265,17 @@ pub(crate) struct SocketStack {
     next_local_port: u16,
 }
 
-fn to_smoltcp_hardware_address(addr: driver::HardwareAddress) -> HardwareAddress {
+fn to_smoltcp_hardware_address(addr: driver::HardwareAddress) -> (HardwareAddress, Medium) {
     match addr {
         #[cfg(feature = "medium-ethernet")]
-        driver::HardwareAddress::Ethernet(eth) => HardwareAddress::Ethernet(EthernetAddress(eth)),
+        driver::HardwareAddress::Ethernet(eth) => (HardwareAddress::Ethernet(EthernetAddress(eth)), Medium::Ethernet),
         #[cfg(feature = "medium-ieee802154")]
-        driver::HardwareAddress::Ieee802154(ieee) => HardwareAddress::Ieee802154(Ieee802154Address::Extended(ieee)),
+        driver::HardwareAddress::Ieee802154(ieee) => (
+            HardwareAddress::Ieee802154(Ieee802154Address::Extended(ieee)),
+            Medium::Ieee802154,
+        ),
         #[cfg(feature = "medium-ip")]
-        driver::HardwareAddress::Ip => HardwareAddress::Ip,
+        driver::HardwareAddress::Ip => (HardwareAddress::Ip, Medium::Ip),
 
         #[allow(unreachable_patterns)]
         _ => panic!(
@@ -289,7 +293,8 @@ impl<D: Driver> Stack<D> {
         resources: &'static mut StackResources<SOCK>,
         random_seed: u64,
     ) -> Self {
-        let mut iface_cfg = smoltcp::iface::Config::new(to_smoltcp_hardware_address(device.hardware_address()));
+        let (hardware_addr, medium) = to_smoltcp_hardware_address(device.hardware_address());
+        let mut iface_cfg = smoltcp::iface::Config::new(hardware_addr);
         iface_cfg.random_seed = random_seed;
 
         let iface = Interface::new(
@@ -297,6 +302,7 @@ impl<D: Driver> Stack<D> {
             &mut DriverAdapter {
                 inner: &mut device,
                 cx: None,
+                medium,
             },
             instant_to_smoltcp(Instant::now()),
         );
@@ -356,7 +362,7 @@ impl<D: Driver> Stack<D> {
 
     /// Get the hardware address of the network interface.
     pub fn hardware_address(&self) -> HardwareAddress {
-        self.with(|_s, i| to_smoltcp_hardware_address(i.device.hardware_address()))
+        self.with(|_s, i| to_smoltcp_hardware_address(i.device.hardware_address()).0)
     }
 
     /// Get whether the link is up.
@@ -812,18 +818,28 @@ impl<D: Driver> Inner<D> {
     fn poll(&mut self, cx: &mut Context<'_>, s: &mut SocketStack) {
         s.waker.register(cx.waker());
 
+        let (_hardware_addr, medium) = to_smoltcp_hardware_address(self.device.hardware_address());
+
         #[cfg(any(feature = "medium-ethernet", feature = "medium-ieee802154"))]
-        if self.device.capabilities().medium == embassy_net_driver::Medium::Ethernet
-            || self.device.capabilities().medium == embassy_net_driver::Medium::Ieee802154
         {
-            s.iface
-                .set_hardware_addr(to_smoltcp_hardware_address(self.device.hardware_address()));
+            let do_set = match medium {
+                #[cfg(feature = "medium-ethernet")]
+                Medium::Ethernet => true,
+                #[cfg(feature = "medium-ieee802154")]
+                Medium::Ieee802154 => true,
+                #[allow(unreachable_patterns)]
+                _ => false,
+            };
+            if do_set {
+                s.iface.set_hardware_addr(_hardware_addr);
+            }
         }
 
         let timestamp = instant_to_smoltcp(Instant::now());
         let mut smoldev = DriverAdapter {
             cx: Some(cx),
             inner: &mut self.device,
+            medium,
         };
         s.iface.poll(timestamp, &mut smoldev, &mut s.sockets);
 
@@ -844,6 +860,9 @@ impl<D: Driver> Inner<D> {
             let socket = s.sockets.get_mut::<dhcpv4::Socket>(dhcp_handle);
 
             if self.link_up {
+                if old_link_up != self.link_up {
+                    socket.reset();
+                }
                 match socket.poll() {
                     None => {}
                     Some(dhcpv4::Event::Deconfigured) => {

embassy-rp/src/adc.rs

@@ -213,6 +213,7 @@ impl<'d> Adc<'d, Async> {
         ch: &mut Channel<'_>,
         buf: &mut [W],
         fcs_err: bool,
+        div: u16,
         dma: impl Peripheral<P = impl dma::Channel>,
     ) -> Result<(), Error> {
         let r = Self::regs();
@@ -258,6 +259,7 @@ impl<'d> Adc<'d, Async> {
         // start conversions and wait for dma to finish. we can't report errors early
         // because there's no interrupt to signal them, and inspecting every element
         // of the fifo is too costly to do here.
+        r.div().write_set(|w| w.set_int(div));
         r.cs().write_set(|w| w.set_start_many(true));
         dma.await;
         mem::drop(auto_reset);
@@ -275,9 +277,10 @@ impl<'d> Adc<'d, Async> {
         &mut self,
         ch: &mut Channel<'_>,
         buf: &mut [S],
+        div: u16,
         dma: impl Peripheral<P = impl dma::Channel>,
     ) -> Result<(), Error> {
-        self.read_many_inner(ch, buf, false, dma).await
+        self.read_many_inner(ch, buf, false, div, dma).await
     }
 
     #[inline]
@@ -285,11 +288,12 @@ impl<'d> Adc<'d, Async> {
         &mut self,
         ch: &mut Channel<'_>,
         buf: &mut [Sample],
+        div: u16,
         dma: impl Peripheral<P = impl dma::Channel>,
     ) {
         // errors are reported in individual samples
         let _ = self
-            .read_many_inner(ch, unsafe { mem::transmute::<_, &mut [u16]>(buf) }, true, dma)
+            .read_many_inner(ch, unsafe { mem::transmute::<_, &mut [u16]>(buf) }, true, div, dma)
             .await;
     }
 }

embassy-rp/src/pwm.rs

@@ -10,16 +10,39 @@ use crate::gpio::sealed::Pin as _;
 use crate::gpio::{AnyPin, Pin as GpioPin};
 use crate::{pac, peripherals, RegExt};
 
+/// The configuration of a PWM slice.
+/// Note the period in clock cycles of a slice can be computed as:
+/// `(top + 1) * (phase_correct ? 1 : 2) * divider`
 #[non_exhaustive]
 #[derive(Clone)]
 pub struct Config {
+    /// Inverts the PWM output signal on channel A.
     pub invert_a: bool,
+    /// Inverts the PWM output signal on channel B.
     pub invert_b: bool,
+    /// Enables phase-correct mode for PWM operation.
+    /// In phase-correct mode, the PWM signal is generated in such a way that
+    /// the pulse is always centered regardless of the duty cycle.
+    /// The output frequency is halved when phase-correct mode is enabled.
     pub phase_correct: bool,
+    /// Enables the PWM slice, allowing it to generate an output.
     pub enable: bool,
+    /// A fractional clock divider, represented as a fixed-point number with
+    /// 8 integer bits and 4 fractional bits. It allows precise control over
+    /// the PWM output frequency by gating the PWM counter increment.
+    /// A higher value will result in a slower output frequency.
     pub divider: fixed::FixedU16<fixed::types::extra::U4>,
+    /// The output on channel A goes high when `compare_a` is higher than the
+    /// counter. A compare of 0 will produce an always low output, while a
+    /// compare of `top + 1` will produce an always high output.
     pub compare_a: u16,
+    /// The output on channel B goes high when `compare_b` is higher than the
+    /// counter. A compare of 0 will produce an always low output, while a
+    /// compare of `top + 1` will produce an always high output.
     pub compare_b: u16,
+    /// The point at which the counter wraps, representing the maximum possible
+    /// period. The counter will either wrap to 0 or reverse depending on the
+    /// setting of `phase_correct`.
     pub top: u16,
 }
 
@@ -173,6 +196,9 @@ impl<'d, T: Channel> Pwm<'d, T> {
         });
     }
 
+    /// Advances a slice’s output phase by one count while it is running
+    /// by inserting a pulse into the clock enable. The counter
+    /// will not count faster than once per cycle.
     #[inline]
     pub fn phase_advance(&mut self) {
         let p = self.inner.regs();
@@ -180,6 +206,9 @@ impl<'d, T: Channel> Pwm<'d, T> {
         while p.csr().read().ph_adv() {}
     }
 
+    /// Retards a slice’s output phase by one count while it is running
+    /// by deleting a pulse from the clock enable. The counter will not
+    /// count backward when clock enable is permenantly low.
     #[inline]
     pub fn phase_retard(&mut self) {
         let p = self.inner.regs();

embassy-stm32-wpan/src/mac/driver.rs

@@ -3,7 +3,7 @@
 
 use core::task::Context;
 
-use embassy_net_driver::{Capabilities, HardwareAddress, LinkState, Medium};
+use embassy_net_driver::{Capabilities, HardwareAddress, LinkState};
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::channel::Channel;
 
@@ -60,24 +60,15 @@ impl<'d> embassy_net_driver::Driver for Driver<'d> {
         let mut caps = Capabilities::default();
         caps.max_transmission_unit = MTU;
         // caps.max_burst_size = Some(self.tx.len());
-
-        caps.medium = Medium::Ieee802154;
         caps
     }
 
     fn link_state(&mut self, _cx: &mut Context) -> LinkState {
-        //        if self.phy.poll_link(&mut self.station_management, cx) {
-        //            LinkState::Up
-        //        } else {
-        //            LinkState::Down
-        //        }
-
         LinkState::Down
     }
 
     fn hardware_address(&self) -> HardwareAddress {
         // self.mac_addr
-
         HardwareAddress::Ieee802154([0; 8])
     }
 }

embassy-stm32/Cargo.toml

@@ -58,7 +58,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
 critical-section = "1.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-c20cbde88fdfaef4645361d09df0cb63a4dc6462" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-bcc9b6bf9fa195e91625849efc4ba473d9ace4e9" }
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-c20cbde88fdfaef4645361d09df0cb63a4dc6462", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-bcc9b6bf9fa195e91625849efc4ba473d9ace4e9", default-features = false, features = ["metadata"]}
 
 
 [features]

embassy-stm32/build.rs

@@ -1,4 +1,4 @@
-use std::collections::{HashMap, HashSet};
+use std::collections::{BTreeMap, BTreeSet, HashMap, HashSet};
 use std::fmt::Write as _;
 use std::path::PathBuf;
 use std::{env, fs};
@@ -352,7 +352,7 @@ fn main() {
     // ========
     // Generate DMA IRQs.
 
-    let mut dma_irqs: HashMap<&str, Vec<(&str, &str, &str)>> = HashMap::new();
+    let mut dma_irqs: BTreeMap<&str, Vec<(&str, &str, &str)>> = BTreeMap::new();
 
     for p in METADATA.peripherals {
         if let Some(r) = &p.registers {
@@ -371,22 +371,27 @@ fn main() {
         }
     }
 
-    for (irq, channels) in dma_irqs {
-        let irq = format_ident!("{}", irq);
+    let dma_irqs: TokenStream = dma_irqs
+        .iter()
+        .map(|(irq, channels)| {
+            let irq = format_ident!("{}", irq);
 
-        let xdma = format_ident!("{}", channels[0].0);
-        let channels = channels.iter().map(|(_, dma, ch)| format_ident!("{}_{}", dma, ch));
+            let xdma = format_ident!("{}", channels[0].0);
+            let channels = channels.iter().map(|(_, dma, ch)| format_ident!("{}_{}", dma, ch));
 
-        g.extend(quote! {
-            #[cfg(feature = "rt")]
-            #[crate::interrupt]
-            unsafe fn #irq () {
-                #(
-                    <crate::peripherals::#channels as crate::dma::#xdma::sealed::Channel>::on_irq();
-                )*
+            quote! {
+                #[cfg(feature = "rt")]
+                #[crate::interrupt]
+                unsafe fn #irq () {
+                    #(
+                        <crate::peripherals::#channels as crate::dma::#xdma::sealed::Channel>::on_irq();
+                    )*
+                }
             }
-        });
-    }
+        })
+        .collect();
+
+    g.extend(dma_irqs);
 
     // ========
     // Extract the rcc registers
@@ -433,7 +438,7 @@ fn main() {
     // Generate RccPeripheral impls
 
     let refcounted_peripherals = HashSet::from(["usart", "adc"]);
-    let mut refcount_statics = HashSet::new();
+    let mut refcount_statics = BTreeSet::new();
 
     for p in METADATA.peripherals {
         if !singletons.contains(&p.name.to_string()) {

embassy-stm32/src/gpio.rs

@@ -763,6 +763,13 @@ pub(crate) unsafe fn init(_cs: CriticalSection) {
     <crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable_and_reset_with_cs(_cs);
 
     crate::_generated::init_gpio();
+
+    // Setting this bit is mandatory to use PG[15:2].
+    #[cfg(stm32u5)]
+    crate::pac::PWR.svmcr().modify(|w| {
+        w.set_io2sv(true);
+        w.set_io2vmen(true);
+    });
 }
 
 mod eh02 {

embassy-stm32/src/ipcc.rs

@@ -5,6 +5,7 @@ use core::task::Poll;
 use self::sealed::Instance;
 use crate::interrupt;
 use crate::interrupt::typelevel::Interrupt;
+use crate::pac::rcc::vals::{Lptim1sel, Lptim2sel};
 use crate::peripherals::IPCC;
 use crate::rcc::sealed::RccPeripheral;
 
@@ -273,7 +274,7 @@ fn _configure_pwr() {
 
     // set LPTIM1 & LPTIM2 clock source
     rcc.ccipr().modify(|w| {
-        w.set_lptim1sel(0b00); // PCLK
-        w.set_lptim2sel(0b00); // PCLK
+        w.set_lptim1sel(Lptim1sel::PCLK1);
+        w.set_lptim2sel(Lptim2sel::PCLK1);
     });
 }

embassy-stm32/src/opamp.rs

@@ -101,18 +101,22 @@ pub trait InvertingPin<T: Instance>: sealed::InvertingPin<T> {}
 #[cfg(opamp_f3)]
 macro_rules! impl_opamp_output {
     ($inst:ident, $adc:ident, $ch:expr) => {
-        impl<'d, 'p, P: NonInvertingPin<crate::peripherals::$inst>> crate::adc::sealed::AdcPin<crate::peripherals::$adc>
-            for OpAmpOutput<'d, 'p, crate::peripherals::$inst, P>
-        {
-            fn channel(&self) -> u8 {
-                $ch
-            }
-        }
+        foreach_adc!(
+            ($adc, $common_inst:ident, $adc_clock:ident) => {
+                impl<'d, 'p, P: NonInvertingPin<crate::peripherals::$inst>> crate::adc::sealed::AdcPin<crate::peripherals::$adc>
+                    for OpAmpOutput<'d, 'p, crate::peripherals::$inst, P>
+                {
+                    fn channel(&self) -> u8 {
+                        $ch
+                    }
+                }
 
-        impl<'d, 'p, P: NonInvertingPin<crate::peripherals::$inst>> crate::adc::AdcPin<crate::peripherals::$adc>
-            for OpAmpOutput<'d, 'p, crate::peripherals::$inst, P>
-        {
-        }
+                impl<'d, 'p, P: NonInvertingPin<crate::peripherals::$inst>> crate::adc::AdcPin<crate::peripherals::$adc>
+                    for OpAmpOutput<'d, 'p, crate::peripherals::$inst, P>
+                {
+                }
+            };
+        );
     };
 }
 

embassy-stm32/src/rcc/f0.rs

@@ -127,7 +127,7 @@ pub(crate) unsafe fn init(config: Config) {
     }
 
     if config.usb_pll {
-        RCC.cfgr3().modify(|w| w.set_usbsw(Usbsw::PLLCLK));
+        RCC.cfgr3().modify(|w| w.set_usbsw(Usbsw::PLL1_P));
     }
     // TODO: Option to use CRS (Clock Recovery)
 
@@ -140,7 +140,7 @@ pub(crate) unsafe fn init(config: Config) {
         RCC.cfgr().modify(|w| {
             w.set_ppre(Ppre::from_bits(ppre_bits));
             w.set_hpre(Hpre::from_bits(hpre_bits));
-            w.set_sw(Sw::PLL)
+            w.set_sw(Sw::PLL1_P)
         });
     } else {
         RCC.cfgr().modify(|w| {

embassy-stm32/src/rcc/f1.rs

@@ -169,7 +169,7 @@ pub(crate) unsafe fn init(config: Config) {
         #[cfg(not(rcc_f100))]
         w.set_usbpre(Usbpre::from_bits(usbpre as u8));
         w.set_sw(if pllmul_bits.is_some() {
-            Sw::PLL
+            Sw::PLL1_P
         } else if config.hse.is_some() {
             Sw::HSE
         } else {

embassy-stm32/src/rcc/f2.rs

@@ -256,7 +256,7 @@ pub(crate) unsafe fn init(config: Config) {
         ClockSrc::PLL => {
             RCC.cr().modify(|w| w.set_pllon(true));
             while !RCC.cr().read().pllrdy() {}
-            (pll_clocks.main_freq, Sw::PLL)
+            (pll_clocks.main_freq, Sw::PLL1_P)
         }
     };
     // RM0033 Figure 9. Clock tree suggests max SYSCLK/HCLK is 168 MHz, but datasheet specifies PLL

embassy-stm32/src/rcc/f3.rs

@@ -214,7 +214,7 @@ pub(crate) unsafe fn init(config: Config) {
     // CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
     RCC.cfgr().modify(|w| {
         w.set_sw(match (pll_config, config.hse) {
-            (Some(_), _) => Sw::PLL,
+            (Some(_), _) => Sw::PLL1_P,
             (None, Some(_)) => Sw::HSE,
             (None, None) => Sw::HSI,
         })
@@ -271,7 +271,7 @@ pub(crate) unsafe fn init(config: Config) {
             pll_config.unwrap();
             assert!((pclk2 == sysclk) || (pclk2 * 2u32 == sysclk));
 
-            RCC.cfgr3().modify(|w| w.set_hrtim1sw(Timsw::PLL));
+            RCC.cfgr3().modify(|w| w.set_hrtim1sw(Timsw::PLL1_P));
 
             Some(sysclk * 2u32)
         }

embassy-stm32/src/rcc/f4.rs

@@ -1,400 +0,0 @@
-use crate::pac::rcc::vals::{Hpre, Pllm, Plln, Pllq, Pllr, Ppre, Sw};
-use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::{set_freqs, Clocks};
-use crate::time::Hertz;
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-
-/// Clocks configuration
-#[non_exhaustive]
-#[derive(Default)]
-pub struct Config {
-    pub hse: Option<Hertz>,
-    pub bypass_hse: bool,
-    pub hclk: Option<Hertz>,
-    pub sys_ck: Option<Hertz>,
-    pub pclk1: Option<Hertz>,
-    pub pclk2: Option<Hertz>,
-
-    #[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
-    pub plli2s: Option<Hertz>,
-
-    #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
-    pub pllsai: Option<Hertz>,
-
-    pub pll48: bool,
-    pub ls: super::LsConfig,
-}
-
-#[cfg(stm32f410)]
-fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
-    None
-}
-
-// Not currently implemented, but will be in the future
-#[cfg(any(stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
-fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
-    None
-}
-
-#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423)))]
-fn calculate_sai_i2s_pll_values(vco_in: u32, max_div: u32, target: Option<u32>) -> Option<(u32, u32, u32)> {
-    let min_div = 2;
-    let target = match target {
-        Some(target) => target,
-        None => return None,
-    };
-
-    // We loop through the possible divider values to find the best configuration. Looping
-    // through all possible "N" values would result in more iterations.
-    let (n, outdiv, output, _error) = (min_div..=max_div)
-        .filter_map(|outdiv| {
-            let target_vco_out = match target.checked_mul(outdiv) {
-                Some(x) => x,
-                None => return None,
-            };
-            let n = (target_vco_out + (vco_in >> 1)) / vco_in;
-            let vco_out = vco_in * n;
-            if !(100_000_000..=432_000_000).contains(&vco_out) {
-                return None;
-            }
-            let output = vco_out / outdiv;
-            let error = (output as i32 - target as i32).unsigned_abs();
-            Some((n, outdiv, output, error))
-        })
-        .min_by_key(|(_, _, _, error)| *error)?;
-
-    Some((n, outdiv, output))
-}
-
-#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
-fn setup_i2s_pll(vco_in: u32, plli2s: Option<u32>) -> Option<u32> {
-    let (n, outdiv, output) = calculate_sai_i2s_pll_values(vco_in, 7, plli2s)?;
-
-    RCC.plli2scfgr().modify(|w| {
-        w.set_plli2sn(n as u16);
-        w.set_plli2sr(outdiv as u8);
-        #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
-        w.set_plli2sq(outdiv as u8); //set sai divider same as i2s
-    });
-
-    Some(output)
-}
-
-#[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479)))]
-fn setup_sai_pll(_vco_in: u32, _pllsai: Option<u32>) -> Option<u32> {
-    None
-}
-
-#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
-fn setup_sai_pll(vco_in: u32, pllsai: Option<u32>) -> Option<u32> {
-    let (n, outdiv, output) = calculate_sai_i2s_pll_values(vco_in, 15, pllsai)?;
-
-    RCC.pllsaicfgr().modify(|w| {
-        w.set_pllsain(n as u16);
-        w.set_pllsaiq(outdiv as u8);
-    });
-
-    Some(output)
-}
-
-fn setup_pll(
-    pllsrcclk: u32,
-    use_hse: bool,
-    pllsysclk: Option<u32>,
-    plli2s: Option<u32>,
-    pllsai: Option<u32>,
-    pll48clk: bool,
-) -> PllResults {
-    use crate::pac::rcc::vals::{Pllp, Pllsrc};
-
-    let sysclk = pllsysclk.unwrap_or(pllsrcclk);
-    if pllsysclk.is_none() && !pll48clk {
-        RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)));
-
-        return PllResults {
-            use_pll: false,
-            pllsysclk: None,
-            pll48clk: None,
-            plli2sclk: None,
-            pllsaiclk: None,
-        };
-    }
-    // Input divisor from PLL source clock, must result to frequency in
-    // the range from 1 to 2 MHz
-    let pllm_min = (pllsrcclk + 1_999_999) / 2_000_000;
-    let pllm_max = pllsrcclk / 1_000_000;
-
-    // Sysclk output divisor must be one of 2, 4, 6 or 8
-    let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
-
-    let target_freq = if pll48clk { 48_000_000 } else { sysclk * sysclk_div };
-
-    // Find the lowest pllm value that minimize the difference between
-    // target frequency and the real vco_out frequency.
-    let pllm = unwrap!((pllm_min..=pllm_max).min_by_key(|pllm| {
-        let vco_in = pllsrcclk / pllm;
-        let plln = target_freq / vco_in;
-        target_freq - vco_in * plln
-    }));
-
-    let vco_in = pllsrcclk / pllm;
-    assert!((1_000_000..=2_000_000).contains(&vco_in));
-
-    // Main scaler, must result in >= 100MHz (>= 192MHz for F401)
-    // and <= 432MHz, min 50, max 432
-    let plln = if pll48clk {
-        // try the different valid pllq according to the valid
-        // main scaller values, and take the best
-        let pllq = unwrap!((4..=9).min_by_key(|pllq| {
-            let plln = 48_000_000 * pllq / vco_in;
-            let pll48_diff = 48_000_000 - vco_in * plln / pllq;
-            let sysclk_diff = (sysclk as i32 - (vco_in * plln / sysclk_div) as i32).abs();
-            (pll48_diff, sysclk_diff)
-        }));
-        48_000_000 * pllq / vco_in
-    } else {
-        sysclk * sysclk_div / vco_in
-    };
-
-    let pllp = (sysclk_div / 2) - 1;
-
-    let pllq = (vco_in * plln + 47_999_999) / 48_000_000;
-    let real_pll48clk = vco_in * plln / pllq;
-
-    RCC.pllcfgr().modify(|w| {
-        w.set_pllm(Pllm::from_bits(pllm as u8));
-        w.set_plln(Plln::from_bits(plln as u16));
-        w.set_pllp(Pllp::from_bits(pllp as u8));
-        w.set_pllq(Pllq::from_bits(pllq as u8));
-        w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
-        w.set_pllr(Pllr::from_bits(0));
-    });
-
-    let real_pllsysclk = vco_in * plln / sysclk_div;
-
-    PllResults {
-        use_pll: true,
-        pllsysclk: Some(real_pllsysclk),
-        pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
-        plli2sclk: setup_i2s_pll(vco_in, plli2s),
-        pllsaiclk: setup_sai_pll(vco_in, pllsai),
-    }
-}
-
-fn flash_setup(sysclk: u32) {
-    use crate::pac::flash::vals::Latency;
-
-    // Be conservative with voltage ranges
-    const FLASH_LATENCY_STEP: u32 = 30_000_000;
-
-    critical_section::with(|_| {
-        FLASH
-            .acr()
-            .modify(|w| w.set_latency(Latency::from_bits(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
-    });
-}
-
-pub(crate) unsafe fn init(config: Config) {
-    let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0);
-    let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
-    let sysclk_on_pll = sysclk != pllsrcclk;
-
-    let plls = setup_pll(
-        pllsrcclk,
-        config.hse.is_some(),
-        if sysclk_on_pll { Some(sysclk) } else { None },
-        #[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
-        config.plli2s.map(|i2s| i2s.0),
-        #[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
-        None,
-        #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
-        config.pllsai.map(|sai| sai.0),
-        #[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479)))]
-        None,
-        config.pll48,
-    );
-
-    if config.pll48 {
-        let freq = unwrap!(plls.pll48clk);
-
-        assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
-    }
-
-    let sysclk = if sysclk_on_pll { unwrap!(plls.pllsysclk) } else { sysclk };
-
-    // AHB prescaler
-    let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
-    let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
-        0 => unreachable!(),
-        1 => (Hpre::DIV1, 1),
-        2 => (Hpre::DIV2, 2),
-        3..=5 => (Hpre::DIV4, 4),
-        6..=11 => (Hpre::DIV8, 8),
-        12..=39 => (Hpre::DIV16, 16),
-        40..=95 => (Hpre::DIV64, 64),
-        96..=191 => (Hpre::DIV128, 128),
-        192..=383 => (Hpre::DIV256, 256),
-        _ => (Hpre::DIV512, 512),
-    };
-
-    // Calculate real AHB clock
-    let hclk = sysclk / hpre_div;
-
-    let pclk1 = config
-        .pclk1
-        .map(|p| p.0)
-        .unwrap_or_else(|| core::cmp::min(max::PCLK1_MAX, hclk));
-
-    let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 {
-        0 => unreachable!(),
-        1 => (0b000, 1),
-        2 => (0b100, 2),
-        3..=5 => (0b101, 4),
-        6..=11 => (0b110, 8),
-        _ => (0b111, 16),
-    };
-    let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
-
-    // Calculate real APB1 clock
-    let pclk1 = hclk / ppre1;
-    assert!(pclk1 <= max::PCLK1_MAX);
-
-    let pclk2 = config
-        .pclk2
-        .map(|p| p.0)
-        .unwrap_or_else(|| core::cmp::min(max::PCLK2_MAX, hclk));
-    let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 {
-        0 => unreachable!(),
-        1 => (0b000, 1),
-        2 => (0b100, 2),
-        3..=5 => (0b101, 4),
-        6..=11 => (0b110, 8),
-        _ => (0b111, 16),
-    };
-    let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
-
-    // Calculate real APB2 clock
-    let pclk2 = hclk / ppre2;
-    assert!(pclk2 <= max::PCLK2_MAX);
-
-    flash_setup(sysclk);
-
-    if config.hse.is_some() {
-        RCC.cr().modify(|w| {
-            w.set_hsebyp(config.bypass_hse);
-            w.set_hseon(true);
-        });
-        while !RCC.cr().read().hserdy() {}
-    }
-
-    if plls.use_pll {
-        RCC.cr().modify(|w| w.set_pllon(true));
-
-        if hclk > max::HCLK_OVERDRIVE_FREQUENCY {
-            PWR.cr1().modify(|w| w.set_oden(true));
-            while !PWR.csr1().read().odrdy() {}
-
-            PWR.cr1().modify(|w| w.set_odswen(true));
-            while !PWR.csr1().read().odswrdy() {}
-        }
-
-        while !RCC.cr().read().pllrdy() {}
-    }
-
-    #[cfg(not(stm32f410))]
-    if plls.plli2sclk.is_some() {
-        RCC.cr().modify(|w| w.set_plli2son(true));
-
-        while !RCC.cr().read().plli2srdy() {}
-    }
-
-    #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
-    if plls.pllsaiclk.is_some() {
-        RCC.cr().modify(|w| w.set_pllsaion(true));
-        while !RCC.cr().read().pllsairdy() {}
-    }
-
-    RCC.cfgr().modify(|w| {
-        w.set_ppre2(Ppre::from_bits(ppre2_bits));
-        w.set_ppre1(Ppre::from_bits(ppre1_bits));
-        w.set_hpre(hpre_bits);
-    });
-
-    // Wait for the new prescalers to kick in
-    // "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
-    cortex_m::asm::delay(16);
-
-    RCC.cfgr().modify(|w| {
-        w.set_sw(if sysclk_on_pll {
-            Sw::PLL
-        } else if config.hse.is_some() {
-            Sw::HSE
-        } else {
-            Sw::HSI
-        })
-    });
-
-    let rtc = config.ls.init();
-
-    set_freqs(Clocks {
-        sys: Hertz(sysclk),
-        pclk1: Hertz(pclk1),
-        pclk2: Hertz(pclk2),
-
-        pclk1_tim: Hertz(pclk1 * timer_mul1),
-        pclk2_tim: Hertz(pclk2 * timer_mul2),
-
-        hclk1: Hertz(hclk),
-        hclk2: Hertz(hclk),
-        hclk3: Hertz(hclk),
-
-        pll1_q: plls.pll48clk.map(Hertz),
-
-        #[cfg(not(stm32f410))]
-        plli2s1_q: plls.plli2sclk.map(Hertz),
-        #[cfg(not(stm32f410))]
-        plli2s1_r: None,
-
-        #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
-        pllsai1_q: plls.pllsaiclk.map(Hertz),
-        #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
-        pllsai1_r: None,
-
-        rtc,
-    });
-}
-
-struct PllResults {
-    use_pll: bool,
-    pllsysclk: Option<u32>,
-    pll48clk: Option<u32>,
-    #[allow(dead_code)]
-    plli2sclk: Option<u32>,
-    #[allow(dead_code)]
-    pllsaiclk: Option<u32>,
-}
-
-mod max {
-    #[cfg(stm32f401)]
-    pub(crate) const SYSCLK_MAX: u32 = 84_000_000;
-    #[cfg(any(stm32f405, stm32f407, stm32f415, stm32f417,))]
-    pub(crate) const SYSCLK_MAX: u32 = 168_000_000;
-    #[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
-    pub(crate) const SYSCLK_MAX: u32 = 100_000_000;
-    #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,))]
-    pub(crate) const SYSCLK_MAX: u32 = 180_000_000;
-
-    pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 168_000_000;
-
-    pub(crate) const PCLK1_MAX: u32 = PCLK2_MAX / 2;
-
-    #[cfg(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
-    pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX;
-    #[cfg(not(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,)))]
-    pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
-
-    pub(crate) const PLL_48_CLK: u32 = 48_000_000;
-    pub(crate) const PLL_48_TOLERANCE: u32 = 120_000;
-}

embassy-stm32/src/rcc/f4f7.rs

@@ -0,0 +1,387 @@
+pub use crate::pac::rcc::vals::{
+    Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp, Pllq, Pllr, Pllsrc as PllSource,
+    Ppre as APBPrescaler, Sw as Sysclk,
+};
+use crate::pac::{FLASH, RCC};
+use crate::rcc::{set_freqs, Clocks};
+use crate::time::Hertz;
+
+// TODO: on some F4s, PLLM is shared between all PLLs. Enforce that.
+// TODO: on some F4s, add support for plli2s_src
+//
+//             plli2s  plli2s_m     plli2s_src   pllsai   pllsai_m
+// f401        y       shared
+// f410
+// f411        y       individual
+// f412        y       individual   y
+// f4[12]3     y       individual   y
+// f446        y       individual                y        individual
+// f4[67]9     y       shared                    y        shared
+// f4[23][79]  y       shared                    y        shared
+// f4[01][57]  y       shared
+
+/// HSI speed
+pub const HSI_FREQ: Hertz = Hertz(16_000_000);
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+    /// crystal/ceramic oscillator (HSEBYP=0)
+    Oscillator,
+    /// external analog clock (low swing) (HSEBYP=1)
+    Bypass,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+    /// HSE frequency.
+    pub freq: Hertz,
+    /// HSE mode.
+    pub mode: HseMode,
+}
+
+#[derive(Clone, Copy)]
+pub struct Pll {
+    /// PLL pre-divider (DIVM).
+    pub prediv: PllPreDiv,
+
+    /// PLL multiplication factor.
+    pub mul: PllMul,
+
+    /// PLL P division factor. If None, PLL P output is disabled.
+    pub divp: Option<Pllp>,
+    /// PLL Q division factor. If None, PLL Q output is disabled.
+    pub divq: Option<Pllq>,
+    /// PLL R division factor. If None, PLL R output is disabled.
+    pub divr: Option<Pllr>,
+}
+
+/// Configuration of the core clocks
+#[non_exhaustive]
+pub struct Config {
+    pub hsi: bool,
+    pub hse: Option<Hse>,
+    pub sys: Sysclk,
+
+    pub pll_src: PllSource,
+
+    pub pll: Option<Pll>,
+    #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
+    pub plli2s: Option<Pll>,
+    #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
+    pub pllsai: Option<Pll>,
+
+    pub ahb_pre: AHBPrescaler,
+    pub apb1_pre: APBPrescaler,
+    pub apb2_pre: APBPrescaler,
+
+    pub ls: super::LsConfig,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            hsi: true,
+            hse: None,
+            sys: Sysclk::HSI,
+            pll_src: PllSource::HSI,
+            pll: None,
+            #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
+            plli2s: None,
+            #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
+            pllsai: None,
+
+            ahb_pre: AHBPrescaler::DIV1,
+            apb1_pre: APBPrescaler::DIV1,
+            apb2_pre: APBPrescaler::DIV1,
+
+            ls: Default::default(),
+        }
+    }
+}
+
+pub(crate) unsafe fn init(config: Config) {
+    // always enable overdrive for now. Make it configurable in the future.
+    #[cfg(not(any(
+        stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f405, stm32f407, stm32f415, stm32f417
+    )))]
+    {
+        use crate::pac::PWR;
+        PWR.cr1().modify(|w| w.set_oden(true));
+        while !PWR.csr1().read().odrdy() {}
+
+        PWR.cr1().modify(|w| w.set_odswen(true));
+        while !PWR.csr1().read().odswrdy() {}
+    }
+
+    // Configure HSI
+    let hsi = match config.hsi {
+        false => {
+            RCC.cr().modify(|w| w.set_hsion(false));
+            None
+        }
+        true => {
+            RCC.cr().modify(|w| w.set_hsion(true));
+            while !RCC.cr().read().hsirdy() {}
+            Some(HSI_FREQ)
+        }
+    };
+
+    // Configure HSE
+    let hse = match config.hse {
+        None => {
+            RCC.cr().modify(|w| w.set_hseon(false));
+            None
+        }
+        Some(hse) => {
+            match hse.mode {
+                HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+                HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+            }
+
+            RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
+            RCC.cr().modify(|w| w.set_hseon(true));
+            while !RCC.cr().read().hserdy() {}
+            Some(hse.freq)
+        }
+    };
+
+    // Configure PLLs.
+    let pll_input = PllInput {
+        hse,
+        hsi,
+        source: config.pll_src,
+    };
+    let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
+    #[cfg(any(all(stm32f4, not(any(stm32f410, stm32f429))), stm32f7))]
+    let _plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
+    #[cfg(all(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7), not(stm32f429)))]
+    let _pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
+
+    // Configure sysclk
+    let sys = match config.sys {
+        Sysclk::HSI => unwrap!(hsi),
+        Sysclk::HSE => unwrap!(hse),
+        Sysclk::PLL1_P => unwrap!(pll.p),
+        _ => unreachable!(),
+    };
+
+    let hclk = sys / config.ahb_pre;
+    let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+    let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
+
+    assert!(max::SYSCLK.contains(&sys));
+    assert!(max::HCLK.contains(&hclk));
+    assert!(max::PCLK1.contains(&pclk1));
+    assert!(max::PCLK2.contains(&pclk2));
+
+    let rtc = config.ls.init();
+
+    flash_setup(hclk);
+
+    RCC.cfgr().modify(|w| {
+        w.set_sw(config.sys);
+        w.set_hpre(config.ahb_pre);
+        w.set_ppre1(config.apb1_pre);
+        w.set_ppre2(config.apb2_pre);
+    });
+    while RCC.cfgr().read().sws() != config.sys {}
+
+    set_freqs(Clocks {
+        sys,
+        hclk1: hclk,
+        hclk2: hclk,
+        hclk3: hclk,
+        pclk1,
+        pclk2,
+        pclk1_tim,
+        pclk2_tim,
+        rtc,
+        pll1_q: pll.q,
+        #[cfg(all(rcc_f4, not(any(stm32f410, stm32f429))))]
+        plli2s1_q: _plli2s.q,
+        #[cfg(all(rcc_f4, not(any(stm32f410, stm32f429))))]
+        plli2s1_r: _plli2s.r,
+
+        #[cfg(stm32f429)]
+        plli2s1_q: None,
+        #[cfg(stm32f429)]
+        plli2s1_r: None,
+
+        #[cfg(any(stm32f427, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
+        pllsai1_q: _pllsai.q,
+        #[cfg(any(stm32f427, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
+        pllsai1_r: _pllsai.r,
+
+        #[cfg(stm32f429)]
+        pllsai1_q: None,
+        #[cfg(stm32f429)]
+        pllsai1_r: None,
+    });
+}
+
+struct PllInput {
+    source: PllSource,
+    hsi: Option<Hertz>,
+    hse: Option<Hertz>,
+}
+
+#[derive(Default)]
+#[allow(unused)]
+struct PllOutput {
+    p: Option<Hertz>,
+    q: Option<Hertz>,
+    r: Option<Hertz>,
+}
+
+#[allow(dead_code)]
+#[derive(PartialEq, Eq, Clone, Copy)]
+enum PllInstance {
+    Pll,
+    #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
+    Plli2s,
+    #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
+    Pllsai,
+}
+
+fn pll_enable(instance: PllInstance, enabled: bool) {
+    match instance {
+        PllInstance::Pll => {
+            RCC.cr().modify(|w| w.set_pllon(enabled));
+            while RCC.cr().read().pllrdy() != enabled {}
+        }
+        #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
+        PllInstance::Plli2s => {
+            RCC.cr().modify(|w| w.set_plli2son(enabled));
+            while RCC.cr().read().plli2srdy() != enabled {}
+        }
+        #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
+        PllInstance::Pllsai => {
+            RCC.cr().modify(|w| w.set_pllsaion(enabled));
+            while RCC.cr().read().pllsairdy() != enabled {}
+        }
+    }
+}
+
+fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
+    // Disable PLL
+    pll_enable(instance, false);
+
+    let Some(pll) = config else { return PllOutput::default() };
+
+    let pll_src = match input.source {
+        PllSource::HSE => input.hse,
+        PllSource::HSI => input.hsi,
+    };
+
+    let pll_src = pll_src.unwrap();
+
+    let in_freq = pll_src / pll.prediv;
+    assert!(max::PLL_IN.contains(&in_freq));
+    let vco_freq = in_freq * pll.mul;
+    assert!(max::PLL_VCO.contains(&vco_freq));
+
+    let p = pll.divp.map(|div| vco_freq / div);
+    let q = pll.divq.map(|div| vco_freq / div);
+    let r = pll.divr.map(|div| vco_freq / div);
+
+    macro_rules! write_fields {
+        ($w:ident) => {
+            $w.set_plln(pll.mul);
+            if let Some(divp) = pll.divp {
+                $w.set_pllp(divp);
+            }
+            if let Some(divq) = pll.divq {
+                $w.set_pllq(divq);
+            }
+            if let Some(divr) = pll.divr {
+                $w.set_pllr(divr);
+            }
+        };
+    }
+
+    match instance {
+        PllInstance::Pll => RCC.pllcfgr().write(|w| {
+            w.set_pllm(pll.prediv);
+            w.set_pllsrc(input.source);
+            write_fields!(w);
+        }),
+        #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
+        PllInstance::Plli2s => RCC.plli2scfgr().write(|w| {
+            write_fields!(w);
+        }),
+        #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
+        PllInstance::Pllsai => RCC.pllsaicfgr().write(|w| {
+            write_fields!(w);
+        }),
+    }
+
+    // Enable PLL
+    pll_enable(instance, true);
+
+    PllOutput { p, q, r }
+}
+
+fn flash_setup(clk: Hertz) {
+    use crate::pac::flash::vals::Latency;
+
+    // Be conservative with voltage ranges
+    const FLASH_LATENCY_STEP: u32 = 30_000_000;
+
+    let latency = (clk.0 - 1) / FLASH_LATENCY_STEP;
+    debug!("flash: latency={}", latency);
+
+    let latency = Latency::from_bits(latency as u8);
+    FLASH.acr().write(|w| {
+        w.set_latency(latency);
+    });
+    while FLASH.acr().read().latency() != latency {}
+}
+
+#[cfg(stm32f7)]
+mod max {
+    use core::ops::RangeInclusive;
+
+    use crate::time::Hertz;
+
+    pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(26_000_000);
+    pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
+
+    pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
+    pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
+    pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000 / 4);
+    pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000 / 2);
+
+    pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
+    pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
+}
+
+#[cfg(stm32f4)]
+mod max {
+    use core::ops::RangeInclusive;
+
+    use crate::time::Hertz;
+
+    pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(26_000_000);
+    pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
+
+    #[cfg(stm32f401)]
+    pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(84_000_000);
+    #[cfg(any(stm32f405, stm32f407, stm32f415, stm32f417,))]
+    pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(168_000_000);
+    #[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
+    pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(100_000_000);
+    #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,))]
+    pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(180_000_000);
+
+    pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(SYSCLK.end().0);
+
+    pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(PCLK2.end().0 / 2);
+
+    #[cfg(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
+    pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(HCLK.end().0);
+    #[cfg(not(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,)))]
+    pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(HCLK.end().0 / 2);
+
+    pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
+    pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
+}

embassy-stm32/src/rcc/f7.rs

@@ -1,305 +0,0 @@
-use crate::pac::pwr::vals::Vos;
-use crate::pac::rcc::vals::{Hpre, Pllm, Plln, Pllp, Pllq, Pllsrc, Ppre, Sw};
-use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::{set_freqs, Clocks};
-use crate::time::Hertz;
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-
-/// Clocks configuration
-#[non_exhaustive]
-#[derive(Default)]
-pub struct Config {
-    pub hse: Option<Hertz>,
-    pub bypass_hse: bool,
-    pub hclk: Option<Hertz>,
-    pub sys_ck: Option<Hertz>,
-    pub pclk1: Option<Hertz>,
-    pub pclk2: Option<Hertz>,
-
-    pub pll48: bool,
-    pub ls: super::LsConfig,
-}
-
-fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
-    let sysclk = pllsysclk.unwrap_or(pllsrcclk);
-    if pllsysclk.is_none() && !pll48clk {
-        RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc::from_bits(use_hse as u8)));
-
-        return PllResults {
-            use_pll: false,
-            pllsysclk: None,
-            pll48clk: None,
-        };
-    }
-    // Input divisor from PLL source clock, must result to frequency in
-    // the range from 1 to 2 MHz
-    let pllm_min = (pllsrcclk + 1_999_999) / 2_000_000;
-    let pllm_max = pllsrcclk / 1_000_000;
-
-    // Sysclk output divisor must be one of 2, 4, 6 or 8
-    let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
-
-    let target_freq = if pll48clk { 48_000_000 } else { sysclk * sysclk_div };
-
-    // Find the lowest pllm value that minimize the difference between
-    // target frequency and the real vco_out frequency.
-    let pllm = unwrap!((pllm_min..=pllm_max).min_by_key(|pllm| {
-        let vco_in = pllsrcclk / pllm;
-        let plln = target_freq / vco_in;
-        target_freq - vco_in * plln
-    }));
-
-    let vco_in = pllsrcclk / pllm;
-    assert!((1_000_000..=2_000_000).contains(&vco_in));
-
-    // Main scaler, must result in >= 100MHz (>= 192MHz for F401)
-    // and <= 432MHz, min 50, max 432
-    let plln = if pll48clk {
-        // try the different valid pllq according to the valid
-        // main scaller values, and take the best
-        let pllq = unwrap!((4..=9).min_by_key(|pllq| {
-            let plln = 48_000_000 * pllq / vco_in;
-            let pll48_diff = 48_000_000 - vco_in * plln / pllq;
-            let sysclk_diff = (sysclk as i32 - (vco_in * plln / sysclk_div) as i32).abs();
-            (pll48_diff, sysclk_diff)
-        }));
-        48_000_000 * pllq / vco_in
-    } else {
-        sysclk * sysclk_div / vco_in
-    };
-
-    let pllp = (sysclk_div / 2) - 1;
-
-    let pllq = (vco_in * plln + 47_999_999) / 48_000_000;
-    let real_pll48clk = vco_in * plln / pllq;
-
-    RCC.pllcfgr().modify(|w| {
-        w.set_pllm(Pllm::from_bits(pllm as u8));
-        w.set_plln(Plln::from_bits(plln as u16));
-        w.set_pllp(Pllp::from_bits(pllp as u8));
-        w.set_pllq(Pllq::from_bits(pllq as u8));
-        w.set_pllsrc(Pllsrc::from_bits(use_hse as u8));
-    });
-
-    let real_pllsysclk = vco_in * plln / sysclk_div;
-
-    PllResults {
-        use_pll: true,
-        pllsysclk: Some(real_pllsysclk),
-        pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
-    }
-}
-
-fn flash_setup(sysclk: u32) {
-    use crate::pac::flash::vals::Latency;
-
-    // Be conservative with voltage ranges
-    const FLASH_LATENCY_STEP: u32 = 30_000_000;
-
-    critical_section::with(|_| {
-        FLASH
-            .acr()
-            .modify(|w| w.set_latency(Latency::from_bits(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
-    });
-}
-
-pub(crate) unsafe fn init(config: Config) {
-    if let Some(hse) = config.hse {
-        if config.bypass_hse {
-            assert!((max::HSE_BYPASS_MIN..=max::HSE_BYPASS_MAX).contains(&hse.0));
-        } else {
-            assert!((max::HSE_OSC_MIN..=max::HSE_OSC_MAX).contains(&hse.0));
-        }
-    }
-
-    let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0);
-    let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
-    let sysclk_on_pll = sysclk != pllsrcclk;
-
-    assert!((max::SYSCLK_MIN..=max::SYSCLK_MAX).contains(&sysclk));
-
-    let plls = setup_pll(
-        pllsrcclk,
-        config.hse.is_some(),
-        if sysclk_on_pll { Some(sysclk) } else { None },
-        config.pll48,
-    );
-
-    if config.pll48 {
-        let freq = unwrap!(plls.pll48clk);
-
-        assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
-    }
-
-    let sysclk = if sysclk_on_pll { unwrap!(plls.pllsysclk) } else { sysclk };
-
-    // AHB prescaler
-    let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
-    let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
-        0 => unreachable!(),
-        1 => (Hpre::DIV1, 1),
-        2 => (Hpre::DIV2, 2),
-        3..=5 => (Hpre::DIV4, 4),
-        6..=11 => (Hpre::DIV8, 8),
-        12..=39 => (Hpre::DIV16, 16),
-        40..=95 => (Hpre::DIV64, 64),
-        96..=191 => (Hpre::DIV128, 128),
-        192..=383 => (Hpre::DIV256, 256),
-        _ => (Hpre::DIV512, 512),
-    };
-
-    // Calculate real AHB clock
-    let hclk = sysclk / hpre_div;
-
-    assert!(hclk <= max::HCLK_MAX);
-
-    let pclk1 = config
-        .pclk1
-        .map(|p| p.0)
-        .unwrap_or_else(|| core::cmp::min(max::PCLK1_MAX, hclk));
-
-    let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 {
-        0 => unreachable!(),
-        1 => (0b000, 1),
-        2 => (0b100, 2),
-        3..=5 => (0b101, 4),
-        6..=11 => (0b110, 8),
-        _ => (0b111, 16),
-    };
-    let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
-
-    // Calculate real APB1 clock
-    let pclk1 = hclk / ppre1;
-    assert!((max::PCLK1_MIN..=max::PCLK1_MAX).contains(&pclk1));
-
-    let pclk2 = config
-        .pclk2
-        .map(|p| p.0)
-        .unwrap_or_else(|| core::cmp::min(max::PCLK2_MAX, hclk));
-    let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 {
-        0 => unreachable!(),
-        1 => (0b000, 1),
-        2 => (0b100, 2),
-        3..=5 => (0b101, 4),
-        6..=11 => (0b110, 8),
-        _ => (0b111, 16),
-    };
-    let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
-
-    // Calculate real APB2 clock
-    let pclk2 = hclk / ppre2;
-    assert!((max::PCLK2_MIN..=max::PCLK2_MAX).contains(&pclk2));
-
-    flash_setup(sysclk);
-
-    if config.hse.is_some() {
-        RCC.cr().modify(|w| {
-            w.set_hsebyp(config.bypass_hse);
-            w.set_hseon(true);
-        });
-        while !RCC.cr().read().hserdy() {}
-    }
-
-    if plls.use_pll {
-        RCC.cr().modify(|w| w.set_pllon(false));
-
-        // setup VOSScale
-        let vos_scale = if sysclk <= 144_000_000 {
-            3
-        } else if sysclk <= 168_000_000 {
-            2
-        } else {
-            1
-        };
-        PWR.cr1().modify(|w| {
-            w.set_vos(match vos_scale {
-                3 => Vos::SCALE3,
-                2 => Vos::SCALE2,
-                1 => Vos::SCALE1,
-                _ => panic!("Invalid VOS Scale."),
-            })
-        });
-
-        RCC.cr().modify(|w| w.set_pllon(true));
-
-        if hclk > max::HCLK_OVERDRIVE_FREQUENCY {
-            PWR.cr1().modify(|w| w.set_oden(true));
-            while !PWR.csr1().read().odrdy() {}
-
-            PWR.cr1().modify(|w| w.set_odswen(true));
-            while !PWR.csr1().read().odswrdy() {}
-        }
-
-        while !RCC.cr().read().pllrdy() {}
-    }
-
-    RCC.cfgr().modify(|w| {
-        w.set_ppre2(Ppre::from_bits(ppre2_bits));
-        w.set_ppre1(Ppre::from_bits(ppre1_bits));
-        w.set_hpre(hpre_bits);
-    });
-
-    // Wait for the new prescalers to kick in
-    // "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
-    cortex_m::asm::delay(16);
-
-    RCC.cfgr().modify(|w| {
-        w.set_sw(if sysclk_on_pll {
-            Sw::PLL
-        } else if config.hse.is_some() {
-            Sw::HSE
-        } else {
-            Sw::HSI
-        })
-    });
-
-    let rtc = config.ls.init();
-
-    set_freqs(Clocks {
-        sys: Hertz(sysclk),
-        pclk1: Hertz(pclk1),
-        pclk2: Hertz(pclk2),
-
-        pclk1_tim: Hertz(pclk1 * timer_mul1),
-        pclk2_tim: Hertz(pclk2 * timer_mul2),
-
-        hclk1: Hertz(hclk),
-        hclk2: Hertz(hclk),
-        hclk3: Hertz(hclk),
-
-        pll1_q: plls.pll48clk.map(Hertz),
-
-        rtc,
-    });
-}
-
-struct PllResults {
-    use_pll: bool,
-    pllsysclk: Option<u32>,
-    pll48clk: Option<u32>,
-}
-
-mod max {
-    pub(crate) const HSE_OSC_MIN: u32 = 4_000_000;
-    pub(crate) const HSE_OSC_MAX: u32 = 26_000_000;
-    pub(crate) const HSE_BYPASS_MIN: u32 = 1_000_000;
-    pub(crate) const HSE_BYPASS_MAX: u32 = 50_000_000;
-
-    pub(crate) const HCLK_MAX: u32 = 216_000_000;
-    pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 180_000_000;
-
-    pub(crate) const SYSCLK_MIN: u32 = 12_500_000;
-    pub(crate) const SYSCLK_MAX: u32 = 216_000_000;
-
-    pub(crate) const PCLK1_MIN: u32 = SYSCLK_MIN;
-    pub(crate) const PCLK1_MAX: u32 = SYSCLK_MAX / 4;
-
-    pub(crate) const PCLK2_MIN: u32 = SYSCLK_MIN;
-    pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
-
-    // USB specification allows +-0.25%
-    pub(crate) const PLL_48_CLK: u32 = 48_000_000;
-    pub(crate) const PLL_48_TOLERANCE: u32 = 120_000;
-}

embassy-stm32/src/rcc/g0.rs

@@ -1,7 +1,7 @@
 use crate::pac::flash::vals::Latency;
 use crate::pac::rcc::vals::{self, Sw};
 pub use crate::pac::rcc::vals::{
-    Hpre as AHBPrescaler, Hsidiv as HSI16Prescaler, Pllm, Plln, Pllp, Pllq, Pllr, Ppre as APBPrescaler,
+    Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Pllm, Plln, Pllp, Pllq, Pllr, Ppre as APBPrescaler,
 };
 use crate::pac::{FLASH, PWR, RCC};
 use crate::rcc::{set_freqs, Clocks};
@@ -14,7 +14,7 @@ pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
     HSE(Hertz),
-    HSI16(HSI16Prescaler),
+    HSI(HSIPrescaler),
     PLL(PllConfig),
     LSI,
 }
@@ -46,9 +46,9 @@ pub struct PllConfig {
 impl Default for PllConfig {
     #[inline]
     fn default() -> PllConfig {
-        // HSI16 / 1 * 8 / 2 = 64 MHz
+        // HSI / 1 * 8 / 2 = 64 MHz
         PllConfig {
-            source: PllSrc::HSI16,
+            source: PllSrc::HSI,
             m: Pllm::DIV1,
             n: Plln::MUL8,
             r: Pllr::DIV2,
@@ -60,7 +60,7 @@ impl Default for PllConfig {
 
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum PllSrc {
-    HSI16,
+    HSI,
     HSE(Hertz),
 }
 
@@ -77,7 +77,7 @@ impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            mux: ClockSrc::HSI16(HSI16Prescaler::DIV1),
+            mux: ClockSrc::HSI(HSIPrescaler::DIV1),
             ahb_pre: AHBPrescaler::DIV1,
             apb_pre: APBPrescaler::DIV1,
             low_power_run: false,
@@ -89,7 +89,7 @@ impl Default for Config {
 impl PllConfig {
     pub(crate) fn init(self) -> Hertz {
         let (src, input_freq) = match self.source {
-            PllSrc::HSI16 => (vals::Pllsrc::HSI, HSI_FREQ),
+            PllSrc::HSI => (vals::Pllsrc::HSI, HSI_FREQ),
             PllSrc::HSE(freq) => (vals::Pllsrc::HSE, freq),
         };
 
@@ -121,7 +121,7 @@ impl PllConfig {
         // > 3. Change the desired parameter.
         // Enable whichever clock source we're using, and wait for it to become ready
         match self.source {
-            PllSrc::HSI16 => {
+            PllSrc::HSI => {
                 RCC.cr().write(|w| w.set_hsion(true));
                 while !RCC.cr().read().hsirdy() {}
             }
@@ -167,8 +167,8 @@ impl PllConfig {
 
 pub(crate) unsafe fn init(config: Config) {
     let (sys_clk, sw) = match config.mux {
-        ClockSrc::HSI16(div) => {
-            // Enable HSI16
+        ClockSrc::HSI(div) => {
+            // Enable HSI
             RCC.cr().write(|w| {
                 w.set_hsidiv(div);
                 w.set_hsion(true)

embassy-stm32/src/rcc/g4.rs

@@ -18,14 +18,14 @@ pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
     HSE(Hertz),
-    HSI16,
+    HSI,
     PLL,
 }
 
 /// PLL clock input source
 #[derive(Clone, Copy, Debug)]
 pub enum PllSrc {
-    HSI16,
+    HSI,
     HSE(Hertz),
 }
 
@@ -33,7 +33,7 @@ impl Into<Pllsrc> for PllSrc {
     fn into(self) -> Pllsrc {
         match self {
             PllSrc::HSE(..) => Pllsrc::HSE,
-            PllSrc::HSI16 => Pllsrc::HSI,
+            PllSrc::HSI => Pllsrc::HSI,
         }
     }
 }
@@ -112,7 +112,7 @@ impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            mux: ClockSrc::HSI16,
+            mux: ClockSrc::HSI,
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
@@ -135,7 +135,7 @@ pub struct PllFreq {
 pub(crate) unsafe fn init(config: Config) {
     let pll_freq = config.pll.map(|pll_config| {
         let src_freq = match pll_config.source {
-            PllSrc::HSI16 => {
+            PllSrc::HSI => {
                 RCC.cr().write(|w| w.set_hsion(true));
                 while !RCC.cr().read().hsirdy() {}
 
@@ -196,8 +196,8 @@ pub(crate) unsafe fn init(config: Config) {
     });
 
     let (sys_clk, sw) = match config.mux {
-        ClockSrc::HSI16 => {
-            // Enable HSI16
+        ClockSrc::HSI => {
+            // Enable HSI
             RCC.cr().write(|w| w.set_hsion(true));
             while !RCC.cr().read().hsirdy() {}
 

embassy-stm32/src/rcc/h.rs

@@ -6,8 +6,11 @@ use crate::pac::pwr::vals::Vos;
 pub use crate::pac::rcc::vals::Adcdacsel as AdcClockSource;
 #[cfg(stm32h7)]
 pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
-use crate::pac::rcc::vals::{Ckpersel, Hsidiv, Pllrge, Pllsrc, Pllvcosel, Sw, Timpre};
-pub use crate::pac::rcc::vals::{Ckpersel as PerClockSource, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul};
+pub use crate::pac::rcc::vals::{
+    Ckpersel as PerClockSource, Hsidiv as HSIPrescaler, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
+    Pllsrc as PllSource, Sw as Sysclk,
+};
+use crate::pac::rcc::vals::{Ckpersel, Pllrge, Pllvcosel, Timpre};
 use crate::pac::{FLASH, PWR, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
@@ -58,50 +61,9 @@ pub struct Hse {
     pub mode: HseMode,
 }
 
-#[cfg(stm32h7)]
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub enum Lse {
-    /// 32.768 kHz crystal/ceramic oscillator (LSEBYP=0)
-    Oscillator,
-    /// external clock input up to 1MHz (LSEBYP=1)
-    Bypass(Hertz),
-}
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub enum Hsi {
-    /// 64Mhz
-    Mhz64,
-    /// 32Mhz (divided by 2)
-    Mhz32,
-    /// 16Mhz (divided by 4)
-    Mhz16,
-    /// 8Mhz (divided by 8)
-    Mhz8,
-}
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub enum Sysclk {
-    /// HSI selected as sysclk
-    HSI,
-    /// HSE selected as sysclk
-    HSE,
-    /// CSI selected as sysclk
-    CSI,
-    /// PLL1_P selected as sysclk
-    Pll1P,
-}
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub enum PllSource {
-    Hsi,
-    Csi,
-    Hse,
-}
-
 #[derive(Clone, Copy)]
 pub struct Pll {
     /// Source clock selection.
-    #[cfg(stm32h5)]
     pub source: PllSource,
 
     /// PLL pre-divider (DIVM).
@@ -161,15 +123,12 @@ impl From<TimerPrescaler> for Timpre {
 /// Configuration of the core clocks
 #[non_exhaustive]
 pub struct Config {
-    pub hsi: Option<Hsi>,
+    pub hsi: Option<HSIPrescaler>,
     pub hse: Option<Hse>,
     pub csi: bool,
     pub hsi48: bool,
     pub sys: Sysclk,
 
-    #[cfg(stm32h7)]
-    pub pll_src: PllSource,
-
     pub pll1: Option<Pll>,
     pub pll2: Option<Pll>,
     #[cfg(any(rcc_h5, stm32h7))]
@@ -193,13 +152,11 @@ pub struct Config {
 impl Default for Config {
     fn default() -> Self {
         Self {
-            hsi: Some(Hsi::Mhz64),
+            hsi: Some(HSIPrescaler::DIV1),
             hse: None,
             csi: false,
             hsi48: false,
             sys: Sysclk::HSI,
-            #[cfg(stm32h7)]
-            pll_src: PllSource::Hsi,
             pll1: None,
             pll2: None,
             #[cfg(any(rcc_h5, stm32h7))]
@@ -312,19 +269,13 @@ pub(crate) unsafe fn init(config: Config) {
             RCC.cr().modify(|w| w.set_hsion(false));
             None
         }
-        Some(hsi) => {
-            let (freq, hsidiv) = match hsi {
-                Hsi::Mhz64 => (HSI_FREQ / 1u32, Hsidiv::DIV1),
-                Hsi::Mhz32 => (HSI_FREQ / 2u32, Hsidiv::DIV2),
-                Hsi::Mhz16 => (HSI_FREQ / 4u32, Hsidiv::DIV4),
-                Hsi::Mhz8 => (HSI_FREQ / 8u32, Hsidiv::DIV8),
-            };
+        Some(hsidiv) => {
             RCC.cr().modify(|w| {
                 w.set_hsidiv(hsidiv);
                 w.set_hsion(true);
             });
             while !RCC.cr().read().hsirdy() {}
-            Some(freq)
+            Some(HSI_FREQ / hsidiv)
         }
     };
 
@@ -369,25 +320,29 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
+    // H7 has shared PLLSRC, check it's equal in all PLLs.
+    #[cfg(stm32h7)]
+    {
+        let plls = [&config.pll1, &config.pll2, &config.pll3];
+        if !super::util::all_equal(plls.into_iter().flatten().map(|p| p.source)) {
+            panic!("Source must be equal across all enabled PLLs.")
+        };
+    }
+
     // Configure PLLs.
-    let pll_input = PllInput {
-        csi,
-        hse,
-        hsi,
-        #[cfg(stm32h7)]
-        source: config.pll_src,
-    };
+    let pll_input = PllInput { csi, hse, hsi };
     let pll1 = init_pll(0, config.pll1, &pll_input);
     let pll2 = init_pll(1, config.pll2, &pll_input);
     #[cfg(any(rcc_h5, stm32h7))]
     let pll3 = init_pll(2, config.pll3, &pll_input);
 
     // Configure sysclk
-    let (sys, sw) = match config.sys {
-        Sysclk::HSI => (unwrap!(hsi), Sw::HSI),
-        Sysclk::HSE => (unwrap!(hse), Sw::HSE),
-        Sysclk::CSI => (unwrap!(csi), Sw::CSI),
-        Sysclk::Pll1P => (unwrap!(pll1.p), Sw::PLL1_P),
+    let sys = match config.sys {
+        Sysclk::HSI => unwrap!(hsi),
+        Sysclk::HSE => unwrap!(hse),
+        Sysclk::CSI => unwrap!(csi),
+        Sysclk::PLL1_P => unwrap!(pll1.p),
+        _ => unreachable!(),
     };
 
     // Check limits.
@@ -398,7 +353,14 @@ pub(crate) unsafe fn init(config: Config) {
         VoltageScale::Scale2 => (Hertz(150_000_000), Hertz(150_000_000)),
         VoltageScale::Scale3 => (Hertz(100_000_000), Hertz(100_000_000)),
     };
-    #[cfg(stm32h7)]
+    #[cfg(pwr_h7rm0455)]
+    let (d1cpre_clk_max, hclk_max, pclk_max) = match config.voltage_scale {
+        VoltageScale::Scale0 => (Hertz(280_000_000), Hertz(280_000_000), Hertz(140_000_000)),
+        VoltageScale::Scale1 => (Hertz(225_000_000), Hertz(225_000_000), Hertz(112_500_000)),
+        VoltageScale::Scale2 => (Hertz(160_000_000), Hertz(160_000_000), Hertz(80_000_000)),
+        VoltageScale::Scale3 => (Hertz(88_000_000), Hertz(88_000_000), Hertz(44_000_000)),
+    };
+    #[cfg(all(stm32h7, not(pwr_h7rm0455)))]
     let (d1cpre_clk_max, hclk_max, pclk_max) = match config.voltage_scale {
         VoltageScale::Scale0 => (Hertz(480_000_000), Hertz(240_000_000), Hertz(120_000_000)),
         VoltageScale::Scale1 => (Hertz(400_000_000), Hertz(200_000_000), Hertz(100_000_000)),
@@ -504,8 +466,8 @@ pub(crate) unsafe fn init(config: Config) {
 
     RCC.cfgr().modify(|w| w.set_timpre(config.timer_prescaler.into()));
 
-    RCC.cfgr().modify(|w| w.set_sw(sw));
-    while RCC.cfgr().read().sws() != sw {}
+    RCC.cfgr().modify(|w| w.set_sw(config.sys));
+    while RCC.cfgr().read().sws() != config.sys {}
 
     // IO compensation cell - Requires CSI clock and SYSCFG
     #[cfg(stm32h7)] // TODO h5
@@ -590,8 +552,6 @@ struct PllInput {
     hsi: Option<Hertz>,
     hse: Option<Hertz>,
     csi: Option<Hertz>,
-    #[cfg(stm32h7)]
-    source: PllSource,
 }
 
 struct PllOutput {
@@ -621,15 +581,11 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
         };
     };
 
-    #[cfg(stm32h5)]
-    let source = config.source;
-    #[cfg(stm32h7)]
-    let source = input.source;
-
-    let (in_clk, src) = match source {
-        PllSource::Hsi => (unwrap!(input.hsi), Pllsrc::HSI),
-        PllSource::Hse => (unwrap!(input.hse), Pllsrc::HSE),
-        PllSource::Csi => (unwrap!(input.csi), Pllsrc::CSI),
+    let in_clk = match config.source {
+        PllSource::DISABLE => panic!("must not set PllSource::Disable"),
+        PllSource::HSI => unwrap!(input.hsi),
+        PllSource::HSE => unwrap!(input.hse),
+        PllSource::CSI => unwrap!(input.csi),
     };
 
     let ref_clk = in_clk / config.prediv as u32;
@@ -669,7 +625,7 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
 
     #[cfg(stm32h5)]
     RCC.pllcfgr(num).write(|w| {
-        w.set_pllsrc(src);
+        w.set_pllsrc(config.source);
         w.set_divm(config.prediv);
         w.set_pllvcosel(vco_range);
         w.set_pllrge(ref_range);
@@ -683,7 +639,7 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
     {
         RCC.pllckselr().modify(|w| {
             w.set_divm(num, config.prediv);
-            w.set_pllsrc(src);
+            w.set_pllsrc(config.source);
         });
         RCC.pllcfgr().modify(|w| {
             w.set_pllvcosel(num, vco_range);

embassy-stm32/src/rcc/l0l1.rs

@@ -18,20 +18,20 @@ pub enum ClockSrc {
     MSI(MSIRange),
     PLL(PLLSource, PLLMul, PLLDiv),
     HSE(Hertz),
-    HSI16,
+    HSI,
 }
 
 /// PLL clock input source
 #[derive(Clone, Copy)]
 pub enum PLLSource {
-    HSI16,
+    HSI,
     HSE(Hertz),
 }
 
 impl From<PLLSource> for Pllsrc {
     fn from(val: PLLSource) -> Pllsrc {
         match val {
-            PLLSource::HSI16 => Pllsrc::HSI,
+            PLLSource::HSI => Pllsrc::HSI,
             PLLSource::HSE(_) => Pllsrc::HSE,
         }
     }
@@ -83,10 +83,10 @@ pub(crate) unsafe fn init(config: Config) {
             let freq = 32_768 * (1 << (range as u8 + 1));
             (Hertz(freq), Sw::MSI)
         }
-        ClockSrc::HSI16 => {
-            // Enable HSI16
-            RCC.cr().write(|w| w.set_hsi16on(true));
-            while !RCC.cr().read().hsi16rdy() {}
+        ClockSrc::HSI => {
+            // Enable HSI
+            RCC.cr().write(|w| w.set_hsion(true));
+            while !RCC.cr().read().hsirdy() {}
 
             (HSI_FREQ, Sw::HSI)
         }
@@ -105,10 +105,10 @@ pub(crate) unsafe fn init(config: Config) {
                     while !RCC.cr().read().hserdy() {}
                     freq
                 }
-                PLLSource::HSI16 => {
+                PLLSource::HSI => {
                     // Enable HSI
-                    RCC.cr().write(|w| w.set_hsi16on(true));
-                    while !RCC.cr().read().hsi16rdy() {}
+                    RCC.cr().write(|w| w.set_hsion(true));
+                    while !RCC.cr().read().hsirdy() {}
                     HSI_FREQ
                 }
             };
@@ -131,7 +131,7 @@ pub(crate) unsafe fn init(config: Config) {
             RCC.cr().modify(|w| w.set_pllon(true));
             while !RCC.cr().read().pllrdy() {}
 
-            (freq, Sw::PLL)
+            (freq, Sw::PLL1_P)
         }
     };
 
@@ -156,23 +156,9 @@ pub(crate) unsafe fn init(config: Config) {
         w.set_ppre2(config.apb2_pre);
     });
 
-    let ahb_freq = sys_clk / config.ahb_pre;
-
-    let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let freq = ahb_freq / pre;
-            (freq, freq * 2u32)
-        }
-    };
-
-    let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let freq = ahb_freq / pre;
-            (freq, freq * 2u32)
-        }
-    };
+    let hclk1 = sys_clk / config.ahb_pre;
+    let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk1, config.apb1_pre);
+    let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk1, config.apb2_pre);
 
     #[cfg(crs)]
     if config.enable_hsi48 {
@@ -209,11 +195,11 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        hclk1: ahb_freq,
-        pclk1: apb1_freq,
-        pclk2: apb2_freq,
-        pclk1_tim: apb1_tim_freq,
-        pclk2_tim: apb2_tim_freq,
+        hclk1,
+        pclk1,
+        pclk2,
+        pclk1_tim,
+        pclk2_tim,
         rtc,
     });
 }

embassy-stm32/src/rcc/l4l5.rs

@@ -1,8 +1,11 @@
 use crate::pac::rcc::regs::Cfgr;
-use crate::pac::rcc::vals::Msirgsel;
+#[cfg(any(stm32l4, stm32l5, stm32wb))]
+pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
+#[cfg(any(stm32wb, stm32wl))]
+pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
 pub use crate::pac::rcc::vals::{
-    Clk48sel as Clk48Src, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul,
-    Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
+    Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv,
+    Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
 };
 use crate::pac::{FLASH, RCC};
 use crate::rcc::{set_freqs, Clocks};
@@ -11,6 +14,25 @@ use crate::time::Hertz;
 /// HSI speed
 pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+    /// crystal/ceramic oscillator (HSEBYP=0)
+    Oscillator,
+    /// external analog clock (low swing) (HSEBYP=1)
+    Bypass,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+    /// HSE frequency.
+    pub freq: Hertz,
+    /// HSE mode.
+    pub mode: HseMode,
+    /// HSE prescaler
+    #[cfg(any(stm32wb, stm32wl))]
+    pub prescaler: HsePrescaler,
+}
+
 #[derive(Clone, Copy)]
 pub struct Pll {
     /// PLL source
@@ -34,13 +56,14 @@ pub struct Pll {
 pub struct Config {
     // base clock sources
     pub msi: Option<MSIRange>,
-    pub hsi16: bool,
-    pub hse: Option<Hertz>,
-    #[cfg(not(any(stm32l47x, stm32l48x)))]
+    pub hsi: bool,
+    pub hse: Option<Hse>,
+    #[cfg(any(all(stm32l4, not(any(stm32l47x, stm32l48x))), stm32l5, stm32wb))]
     pub hsi48: bool,
 
     // pll
     pub pll: Option<Pll>,
+    #[cfg(any(stm32l4, stm32l5, stm32wb))]
     pub pllsai1: Option<Pll>,
     #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
     pub pllsai2: Option<Pll>,
@@ -50,8 +73,13 @@ pub struct Config {
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
+    #[cfg(any(stm32wl5x, stm32wb))]
+    pub core2_ahb_pre: AHBPrescaler,
+    #[cfg(any(stm32wl, stm32wb))]
+    pub shared_ahb_pre: AHBPrescaler,
 
     // muxes
+    #[cfg(any(stm32l4, stm32l5, stm32wb))]
     pub clk48_src: Clk48Src,
 
     // low speed LSI/LSE/RTC
@@ -63,30 +91,69 @@ impl Default for Config {
     fn default() -> Config {
         Config {
             hse: None,
-            hsi16: false,
+            hsi: false,
             msi: Some(MSIRange::RANGE4M),
             mux: ClockSrc::MSI,
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
+            #[cfg(any(stm32wl5x, stm32wb))]
+            core2_ahb_pre: AHBPrescaler::DIV1,
+            #[cfg(any(stm32wl, stm32wb))]
+            shared_ahb_pre: AHBPrescaler::DIV1,
             pll: None,
+            #[cfg(any(stm32l4, stm32l5, stm32wb))]
             pllsai1: None,
             #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
             pllsai2: None,
-            #[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
+            #[cfg(any(all(stm32l4, not(any(stm32l47x, stm32l48x))), stm32l5, stm32wb))]
             hsi48: true,
+            #[cfg(any(stm32l4, stm32l5, stm32wb))]
             clk48_src: Clk48Src::HSI48,
             ls: Default::default(),
         }
     }
 }
 
+#[cfg(stm32wb)]
+pub const WPAN_DEFAULT: Config = Config {
+    hse: Some(Hse {
+        freq: Hertz(32_000_000),
+        mode: HseMode::Oscillator,
+        prescaler: HsePrescaler::DIV1,
+    }),
+    mux: ClockSrc::PLL1_R,
+    hsi48: true,
+    msi: None,
+    hsi: false,
+    clk48_src: Clk48Src::PLL1_Q,
+
+    ls: super::LsConfig::default_lse(),
+
+    pll: Some(Pll {
+        source: PLLSource::HSE,
+        prediv: PllPreDiv::DIV2,
+        mul: PllMul::MUL12,
+        divp: Some(PllPDiv::DIV3), // 32 / 2 * 12 / 3 = 64Mhz
+        divq: Some(PllQDiv::DIV4), // 32 / 2 * 12 / 4 = 48Mhz
+        divr: Some(PllRDiv::DIV3), // 32 / 2 * 12 / 3 = 64Mhz
+    }),
+    pllsai1: None,
+
+    ahb_pre: AHBPrescaler::DIV1,
+    core2_ahb_pre: AHBPrescaler::DIV2,
+    shared_ahb_pre: AHBPrescaler::DIV1,
+    apb1_pre: APBPrescaler::DIV1,
+    apb2_pre: APBPrescaler::DIV1,
+};
+
 pub(crate) unsafe fn init(config: Config) {
     // Switch to MSI to prevent problems with PLL configuration.
     if !RCC.cr().read().msion() {
         // Turn on MSI and configure it to 4MHz.
         RCC.cr().modify(|w| {
-            w.set_msirgsel(Msirgsel::CR);
+            #[cfg(not(stm32wb))]
+            w.set_msirgsel(crate::pac::rcc::vals::Msirgsel::CR);
             w.set_msirange(MSIRange::RANGE4M);
             w.set_msipllen(false);
             w.set_msion(true)
@@ -111,9 +178,10 @@ pub(crate) unsafe fn init(config: Config) {
 
     let msi = config.msi.map(|range| {
         // Enable MSI
-        RCC.cr().write(|w| {
+        RCC.cr().modify(|w| {
+            #[cfg(not(stm32wb))]
+            w.set_msirgsel(crate::pac::rcc::vals::Msirgsel::CR);
             w.set_msirange(range);
-            w.set_msirgsel(Msirgsel::CR);
             w.set_msion(true);
 
             // If LSE is enabled, enable calibration of MSI
@@ -127,21 +195,27 @@ pub(crate) unsafe fn init(config: Config) {
         msirange_to_hertz(range)
     });
 
-    let hsi16 = config.hsi16.then(|| {
-        RCC.cr().write(|w| w.set_hsion(true));
+    let hsi = config.hsi.then(|| {
+        RCC.cr().modify(|w| w.set_hsion(true));
         while !RCC.cr().read().hsirdy() {}
 
         HSI_FREQ
     });
 
-    let hse = config.hse.map(|freq| {
-        RCC.cr().write(|w| w.set_hseon(true));
+    let hse = config.hse.map(|hse| {
+        RCC.cr().modify(|w| {
+            #[cfg(stm32wl)]
+            w.set_hsebyppwr(hse.mode == HseMode::Bypass);
+            #[cfg(not(stm32wl))]
+            w.set_hsebyp(hse.mode == HseMode::Bypass);
+            w.set_hseon(true);
+        });
         while !RCC.cr().read().hserdy() {}
 
-        freq
+        hse.freq
     });
 
-    #[cfg(not(any(stm32l47x, stm32l48x)))]
+    #[cfg(any(all(stm32l4, not(any(stm32l47x, stm32l48x))), stm32l5, stm32wb))]
     let hsi48 = config.hsi48.then(|| {
         RCC.crrcr().modify(|w| w.set_hsi48on(true));
         while !RCC.crrcr().read().hsi48rdy() {}
@@ -153,6 +227,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     let _plls = [
         &config.pll,
+        #[cfg(any(stm32l4, stm32l5, stm32wb))]
         &config.pllsai1,
         #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
         &config.pllsai2,
@@ -160,7 +235,7 @@ pub(crate) unsafe fn init(config: Config) {
 
     // L4 has shared PLLSRC, PLLM, check it's equal in all PLLs.
     #[cfg(all(stm32l4, not(rcc_l4plus)))]
-    match get_equal(_plls.into_iter().flatten().map(|p| (p.source, p.prediv))) {
+    match super::util::get_equal(_plls.into_iter().flatten().map(|p| (p.source, p.prediv))) {
         Err(()) => panic!("Source must be equal across all enabled PLLs."),
         Ok(None) => {}
         Ok(Some((source, prediv))) => RCC.pllcfgr().write(|w| {
@@ -169,9 +244,9 @@ pub(crate) unsafe fn init(config: Config) {
         }),
     };
 
-    // L4+ has shared PLLSRC, check it's equal in all PLLs.
-    #[cfg(any(rcc_l4plus))]
-    match get_equal(_plls.into_iter().flatten().map(|p| p.source)) {
+    // L4+, WL has shared PLLSRC, check it's equal in all PLLs.
+    #[cfg(any(rcc_l4plus, stm32wl))]
+    match super::util::get_equal(_plls.into_iter().flatten().map(|p| p.source)) {
         Err(()) => panic!("Source must be equal across all enabled PLLs."),
         Ok(None) => {}
         Ok(Some(source)) => RCC.pllcfgr().write(|w| {
@@ -179,34 +254,30 @@ pub(crate) unsafe fn init(config: Config) {
         }),
     };
 
-    let pll_input = PllInput { hse, hsi16, msi };
+    let pll_input = PllInput { hse, hsi, msi };
     let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
+    #[cfg(any(stm32l4, stm32l5, stm32wb))]
     let pllsai1 = init_pll(PllInstance::Pllsai1, config.pllsai1, &pll_input);
     #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
     let _pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input);
 
     let sys_clk = match config.mux {
         ClockSrc::HSE => hse.unwrap(),
-        #[cfg(rcc_l5)]
-        ClockSrc::HSI16 => hsi16.unwrap(),
-        #[cfg(not(rcc_l5))]
-        ClockSrc::HSI => hsi16.unwrap(),
+        ClockSrc::HSI => hsi.unwrap(),
         ClockSrc::MSI => msi.unwrap(),
-        ClockSrc::PLL => pll._r.unwrap(),
+        ClockSrc::PLL1_R => pll.r.unwrap(),
     };
 
     #[cfg(stm32l4)]
     RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src));
     #[cfg(stm32l5)]
     RCC.ccipr1().modify(|w| w.set_clk48sel(config.clk48_src));
+    #[cfg(any(stm32l4, stm32l5, stm32wb))]
     let _clk48 = match config.clk48_src {
         Clk48Src::HSI48 => hsi48,
         Clk48Src::MSI => msi,
-        Clk48Src::PLLSAI1_Q => pllsai1._q,
-        #[cfg(rcc_l5)]
-        Clk48Src::PLL_Q => pll._q,
-        #[cfg(not(rcc_l5))]
-        Clk48Src::PLL1_Q => pll._q,
+        Clk48Src::PLLSAI1_Q => pllsai1.q,
+        Clk48Src::PLL1_Q => pll.q,
     };
 
     #[cfg(rcc_l4plus)]
@@ -214,29 +285,56 @@ pub(crate) unsafe fn init(config: Config) {
     #[cfg(all(stm32l4, not(rcc_l4plus)))]
     assert!(sys_clk.0 <= 80_000_000);
 
+    let hclk1 = sys_clk / config.ahb_pre;
+    let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk1, config.apb1_pre);
+    let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk1, config.apb2_pre);
+    #[cfg(not(any(stm32wl5x, stm32wb)))]
+    let hclk2 = hclk1;
+    #[cfg(any(stm32wl5x, stm32wb))]
+    let hclk2 = sys_clk / config.core2_ahb_pre;
+    #[cfg(not(any(stm32wl, stm32wb)))]
+    let hclk3 = hclk1;
+    #[cfg(any(stm32wl, stm32wb))]
+    let hclk3 = sys_clk / config.shared_ahb_pre;
+
     // Set flash wait states
     #[cfg(stm32l4)]
-    FLASH.acr().modify(|w| {
-        w.set_latency(match sys_clk.0 {
-            0..=16_000_000 => 0,
-            0..=32_000_000 => 1,
-            0..=48_000_000 => 2,
-            0..=64_000_000 => 3,
-            _ => 4,
-        })
-    });
-    // VCORE Range 0 (performance), others TODO
+    let latency = match hclk1.0 {
+        0..=16_000_000 => 0,
+        0..=32_000_000 => 1,
+        0..=48_000_000 => 2,
+        0..=64_000_000 => 3,
+        _ => 4,
+    };
     #[cfg(stm32l5)]
-    FLASH.acr().modify(|w| {
-        w.set_latency(match sys_clk.0 {
-            0..=20_000_000 => 0,
-            0..=40_000_000 => 1,
-            0..=60_000_000 => 2,
-            0..=80_000_000 => 3,
-            0..=100_000_000 => 4,
-            _ => 5,
-        })
-    });
+    let latency = match hclk1.0 {
+        // VCORE Range 0 (performance), others TODO
+        0..=20_000_000 => 0,
+        0..=40_000_000 => 1,
+        0..=60_000_000 => 2,
+        0..=80_000_000 => 3,
+        0..=100_000_000 => 4,
+        _ => 5,
+    };
+    #[cfg(stm32wl)]
+    let latency = match hclk3.0 {
+        // VOS RANGE1, others TODO.
+        ..=18_000_000 => 0,
+        ..=36_000_000 => 1,
+        _ => 2,
+    };
+    #[cfg(stm32wb)]
+    let latency = match hclk3.0 {
+        // VOS RANGE1, others TODO.
+        ..=18_000_000 => 0,
+        ..=36_000_000 => 1,
+        ..=54_000_000 => 2,
+        ..=64_000_000 => 3,
+        _ => 4,
+    };
+
+    FLASH.acr().modify(|w| w.set_latency(latency));
+    while FLASH.acr().read().latency() != latency {}
 
     RCC.cfgr().modify(|w| {
         w.set_sw(config.mux);
@@ -244,34 +342,31 @@ pub(crate) unsafe fn init(config: Config) {
         w.set_ppre1(config.apb1_pre);
         w.set_ppre2(config.apb2_pre);
     });
+    while RCC.cfgr().read().sws() != config.mux {}
 
-    let ahb_freq = sys_clk / config.ahb_pre;
-
-    let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let freq = ahb_freq / pre;
-            (freq, freq * 2u32)
-        }
-    };
-
-    let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let freq = ahb_freq / pre;
-            (freq, freq * 2u32)
-        }
-    };
+    #[cfg(any(stm32wl, stm32wb))]
+    {
+        RCC.extcfgr().modify(|w| {
+            w.set_shdhpre(config.shared_ahb_pre);
+            #[cfg(any(stm32wl5x, stm32wb))]
+            w.set_c2hpre(config.core2_ahb_pre);
+        });
+        while !RCC.extcfgr().read().shdhpref() {}
+        #[cfg(any(stm32wl5x, stm32wb))]
+        while !RCC.extcfgr().read().c2hpref() {}
+    }
 
     set_freqs(Clocks {
         sys: sys_clk,
-        hclk1: ahb_freq,
-        hclk2: ahb_freq,
-        hclk3: ahb_freq,
-        pclk1: apb1_freq,
-        pclk2: apb2_freq,
-        pclk1_tim: apb1_tim_freq,
-        pclk2_tim: apb2_tim_freq,
+        hclk1,
+        hclk2,
+        hclk3,
+        pclk1,
+        pclk2,
+        pclk1_tim,
+        pclk2_tim,
+        #[cfg(stm32wl)]
+        pclk3: hclk3,
         #[cfg(rcc_l4)]
         hsi: None,
         #[cfg(rcc_l4)]
@@ -310,63 +405,58 @@ fn msirange_to_hertz(range: MSIRange) -> Hertz {
     }
 }
 
-#[allow(unused)]
-fn get_equal<T: Eq>(mut iter: impl Iterator<Item = T>) -> Result<Option<T>, ()> {
-    let Some(x) = iter.next() else { return Ok(None) };
-    if !iter.all(|y| y == x) {
-        return Err(());
-    }
-    return Ok(Some(x));
-}
-
 struct PllInput {
-    hsi16: Option<Hertz>,
+    hsi: Option<Hertz>,
     hse: Option<Hertz>,
     msi: Option<Hertz>,
 }
 
+#[allow(unused)]
 #[derive(Default)]
 struct PllOutput {
-    _p: Option<Hertz>,
-    _q: Option<Hertz>,
-    _r: Option<Hertz>,
+    p: Option<Hertz>,
+    q: Option<Hertz>,
+    r: Option<Hertz>,
 }
 
 #[derive(PartialEq, Eq, Clone, Copy)]
 enum PllInstance {
     Pll,
+    #[cfg(any(stm32l4, stm32l5, stm32wb))]
     Pllsai1,
     #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
     Pllsai2,
 }
 
-fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
-    // Disable PLL
+fn pll_enable(instance: PllInstance, enabled: bool) {
     match instance {
         PllInstance::Pll => {
-            RCC.cr().modify(|w| w.set_pllon(false));
-            while RCC.cr().read().pllrdy() {}
+            RCC.cr().modify(|w| w.set_pllon(enabled));
+            while RCC.cr().read().pllrdy() != enabled {}
         }
+        #[cfg(any(stm32l4, stm32l5, stm32wb))]
         PllInstance::Pllsai1 => {
-            RCC.cr().modify(|w| w.set_pllsai1on(false));
-            while RCC.cr().read().pllsai1rdy() {}
+            RCC.cr().modify(|w| w.set_pllsai1on(enabled));
+            while RCC.cr().read().pllsai1rdy() != enabled {}
         }
         #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
         PllInstance::Pllsai2 => {
-            RCC.cr().modify(|w| w.set_pllsai2on(false));
-            while RCC.cr().read().pllsai2rdy() {}
+            RCC.cr().modify(|w| w.set_pllsai2on(enabled));
+            while RCC.cr().read().pllsai2rdy() != enabled {}
         }
     }
+}
+
+fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
+    // Disable PLL
+    pll_enable(instance, false);
 
     let Some(pll) = config else { return PllOutput::default() };
 
     let pll_src = match pll.source {
-        PLLSource::NONE => panic!("must not select PLL source as NONE"),
+        PLLSource::DISABLE => panic!("must not select PLL source as DISABLE"),
         PLLSource::HSE => input.hse,
-        #[cfg(rcc_l5)]
-        PLLSource::HSI16 => input.hsi16,
-        #[cfg(not(rcc_l5))]
-        PLLSource::HSI => input.hsi16,
+        PLLSource::HSI => input.hsi,
         PLLSource::MSI => input.msi,
     };
 
@@ -408,6 +498,7 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
             w.set_pllsrc(pll.source);
             write_fields!(w);
         }),
+        #[cfg(any(stm32l4, stm32l5, stm32wb))]
         PllInstance::Pllsai1 => RCC.pllsai1cfgr().write(|w| {
             #[cfg(any(rcc_l4plus, stm32l5))]
             w.set_pllm(pll.prediv);
@@ -426,21 +517,7 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
     }
 
     // Enable PLL
-    match instance {
-        PllInstance::Pll => {
-            RCC.cr().modify(|w| w.set_pllon(true));
-            while !RCC.cr().read().pllrdy() {}
-        }
-        PllInstance::Pllsai1 => {
-            RCC.cr().modify(|w| w.set_pllsai1on(true));
-            while !RCC.cr().read().pllsai1rdy() {}
-        }
-        #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
-        PllInstance::Pllsai2 => {
-            RCC.cr().modify(|w| w.set_pllsai2on(true));
-            while !RCC.cr().read().pllsai2rdy() {}
-        }
-    }
+    pll_enable(instance, true);
 
-    PllOutput { _p: p, _q: q, _r: r }
+    PllOutput { p, q, r }
 }

embassy-stm32/src/rcc/mod.rs

@@ -13,18 +13,15 @@ pub use mco::*;
 #[cfg_attr(any(rcc_f1, rcc_f100, rcc_f1cl), path = "f1.rs")]
 #[cfg_attr(rcc_f2, path = "f2.rs")]
 #[cfg_attr(any(rcc_f3, rcc_f3_v2), path = "f3.rs")]
-#[cfg_attr(any(rcc_f4, rcc_f410), path = "f4.rs")]
-#[cfg_attr(rcc_f7, path = "f7.rs")]
+#[cfg_attr(any(rcc_f4, rcc_f410, rcc_f7), path = "f4f7.rs")]
 #[cfg_attr(rcc_c0, path = "c0.rs")]
 #[cfg_attr(rcc_g0, path = "g0.rs")]
 #[cfg_attr(rcc_g4, path = "g4.rs")]
 #[cfg_attr(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab), path = "h.rs")]
 #[cfg_attr(any(rcc_l0, rcc_l0_v2, rcc_l1), path = "l0l1.rs")]
-#[cfg_attr(any(rcc_l4, rcc_l4plus, rcc_l5), path = "l4l5.rs")]
+#[cfg_attr(any(rcc_l4, rcc_l4plus, rcc_l5, rcc_wl5, rcc_wle, rcc_wb), path = "l4l5.rs")]
 #[cfg_attr(rcc_u5, path = "u5.rs")]
-#[cfg_attr(rcc_wb, path = "wb.rs")]
 #[cfg_attr(rcc_wba, path = "wba.rs")]
-#[cfg_attr(any(rcc_wl5, rcc_wle), path = "wl.rs")]
 mod _version;
 #[cfg(feature = "low-power")]
 use core::sync::atomic::{AtomicU32, Ordering};
@@ -249,3 +246,33 @@ pub(crate) mod sealed {
 }
 
 pub trait RccPeripheral: sealed::RccPeripheral + 'static {}
+
+#[allow(unused)]
+mod util {
+    use crate::time::Hertz;
+
+    pub fn calc_pclk<D>(hclk: Hertz, ppre: D) -> (Hertz, Hertz)
+    where
+        Hertz: core::ops::Div<D, Output = Hertz>,
+    {
+        let pclk = hclk / ppre;
+        let pclk_tim = if hclk == pclk { pclk } else { pclk * 2u32 };
+        (pclk, pclk_tim)
+    }
+
+    pub fn all_equal<T: Eq>(mut iter: impl Iterator<Item = T>) -> bool {
+        let Some(x) = iter.next() else { return true };
+        if !iter.all(|y| y == x) {
+            return false;
+        }
+        true
+    }
+
+    pub fn get_equal<T: Eq>(mut iter: impl Iterator<Item = T>) -> Result<Option<T>, ()> {
+        let Some(x) = iter.next() else { return Ok(None) };
+        if !iter.all(|y| y == x) {
+            return Err(());
+        }
+        Ok(Some(x))
+    }
+}

embassy-stm32/src/rcc/u5.rs

@@ -10,6 +10,7 @@ pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
 
 #[derive(Copy, Clone)]
+#[allow(non_camel_case_types)]
 pub enum ClockSrc {
     /// Use an internal medium speed oscillator (MSIS) as the system clock.
     MSI(Msirange),
@@ -19,9 +20,9 @@ pub enum ClockSrc {
     /// never exceed 50 MHz.
     HSE(Hertz),
     /// Use the 16 MHz internal high speed oscillator as the system clock.
-    HSI16,
+    HSI,
     /// Use PLL1 as the system clock.
-    PLL1R(PllConfig),
+    PLL1_R(PllConfig),
 }
 
 impl Default for ClockSrc {
@@ -53,10 +54,10 @@ pub struct PllConfig {
 }
 
 impl PllConfig {
-    /// A configuration for HSI16 / 1 * 10 / 1 = 160 MHz
-    pub const fn hsi16_160mhz() -> Self {
+    /// A configuration for HSI / 1 * 10 / 1 = 160 MHz
+    pub const fn hsi_160mhz() -> Self {
         PllConfig {
-            source: PllSrc::HSI16,
+            source: PllSrc::HSI,
             m: Pllm::DIV1,
             n: Plln::MUL10,
             r: Plldiv::DIV1,
@@ -84,7 +85,7 @@ pub enum PllSrc {
     /// never exceed 50 MHz.
     HSE(Hertz),
     /// Use the 16 MHz internal high speed oscillator as the PLL source.
-    HSI16,
+    HSI,
 }
 
 impl Into<Pllsrc> for PllSrc {
@@ -92,7 +93,7 @@ impl Into<Pllsrc> for PllSrc {
         match self {
             PllSrc::MSIS(..) => Pllsrc::MSIS,
             PllSrc::HSE(..) => Pllsrc::HSE,
-            PllSrc::HSI16 => Pllsrc::HSI16,
+            PllSrc::HSI => Pllsrc::HSI,
         }
     }
 }
@@ -102,8 +103,8 @@ impl Into<Sw> for ClockSrc {
         match self {
             ClockSrc::MSI(..) => Sw::MSIS,
             ClockSrc::HSE(..) => Sw::HSE,
-            ClockSrc::HSI16 => Sw::HSI16,
-            ClockSrc::PLL1R(..) => Sw::PLL1_R,
+            ClockSrc::HSI => Sw::HSI,
+            ClockSrc::PLL1_R(..) => Sw::PLL1_R,
         }
     }
 }
@@ -125,7 +126,7 @@ pub struct Config {
 }
 
 impl Config {
-    unsafe fn init_hsi16(&self) -> Hertz {
+    unsafe fn init_hsi(&self) -> Hertz {
         RCC.cr().write(|w| w.set_hsion(true));
         while !RCC.cr().read().hsirdy() {}
 
@@ -169,7 +170,7 @@ impl Config {
 
         RCC.icscr1().modify(|w| {
             w.set_msisrange(range);
-            w.set_msirgsel(Msirgsel::RCC_ICSCR1);
+            w.set_msirgsel(Msirgsel::ICSCR1);
         });
         RCC.cr().write(|w| {
             w.set_msipllen(false);
@@ -211,13 +212,13 @@ pub(crate) unsafe fn init(config: Config) {
     let sys_clk = match config.mux {
         ClockSrc::MSI(range) => config.init_msis(range),
         ClockSrc::HSE(freq) => config.init_hse(freq),
-        ClockSrc::HSI16 => config.init_hsi16(),
-        ClockSrc::PLL1R(pll) => {
+        ClockSrc::HSI => config.init_hsi(),
+        ClockSrc::PLL1_R(pll) => {
             // Configure the PLL source
             let source_clk = match pll.source {
                 PllSrc::MSIS(range) => config.init_msis(range),
                 PllSrc::HSE(hertz) => config.init_hse(hertz),
-                PllSrc::HSI16 => config.init_hsi16(),
+                PllSrc::HSI => config.init_hsi(),
             };
 
             // Calculate the reference clock, which is the source divided by m
@@ -292,7 +293,7 @@ pub(crate) unsafe fn init(config: Config) {
                 // Set the prescaler for PWR EPOD
                 w.set_pllmboost(mboost);
 
-                // Enable PLL1R output
+                // Enable PLL1_R output
                 w.set_pllren(true);
             });
 

embassy-stm32/src/rcc/wb.rs

@@ -1,258 +0,0 @@
-pub use crate::pac::rcc::vals::{
-    Hpre as AHBPrescaler, Hsepre as HsePrescaler, Pllm, Plln, Pllp, Pllq, Pllr, Pllsrc as PllSource,
-    Ppre as APBPrescaler, Sw as Sysclk,
-};
-use crate::rcc::{set_freqs, Clocks};
-use crate::time::{mhz, Hertz};
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-
-pub struct Hse {
-    pub prediv: HsePrescaler,
-
-    pub frequency: Hertz,
-}
-
-pub struct PllMux {
-    /// Source clock selection.
-    pub source: PllSource,
-
-    /// PLL pre-divider (DIVM). Must be between 1 and 63.
-    pub prediv: Pllm,
-}
-
-pub struct Pll {
-    /// PLL multiplication factor. Must be between 4 and 512.
-    pub mul: Plln,
-
-    /// PLL P division factor. If None, PLL P output is disabled. Must be between 1 and 128.
-    /// On PLL1, it must be even (in particular, it cannot be 1.)
-    pub divp: Option<Pllp>,
-    /// PLL Q division factor. If None, PLL Q output is disabled. Must be between 1 and 128.
-    pub divq: Option<Pllq>,
-    /// PLL R division factor. If None, PLL R output is disabled. Must be between 1 and 128.
-    pub divr: Option<Pllr>,
-}
-
-/// Clocks configutation
-pub struct Config {
-    pub hse: Option<Hse>,
-    pub sys: Sysclk,
-    pub mux: Option<PllMux>,
-    pub hsi48: bool,
-
-    pub pll: Option<Pll>,
-    pub pllsai: Option<Pll>,
-
-    pub ahb1_pre: AHBPrescaler,
-    pub ahb2_pre: AHBPrescaler,
-    pub ahb3_pre: AHBPrescaler,
-    pub apb1_pre: APBPrescaler,
-    pub apb2_pre: APBPrescaler,
-
-    pub ls: super::LsConfig,
-}
-
-pub const WPAN_DEFAULT: Config = Config {
-    hse: Some(Hse {
-        frequency: mhz(32),
-        prediv: HsePrescaler::DIV1,
-    }),
-    sys: Sysclk::PLL,
-    mux: Some(PllMux {
-        source: PllSource::HSE,
-        prediv: Pllm::DIV2,
-    }),
-    hsi48: true,
-
-    ls: super::LsConfig::default_lse(),
-
-    pll: Some(Pll {
-        mul: Plln::MUL12,
-        divp: Some(Pllp::DIV3),
-        divq: Some(Pllq::DIV4),
-        divr: Some(Pllr::DIV3),
-    }),
-    pllsai: None,
-
-    ahb1_pre: AHBPrescaler::DIV1,
-    ahb2_pre: AHBPrescaler::DIV2,
-    ahb3_pre: AHBPrescaler::DIV1,
-    apb1_pre: APBPrescaler::DIV1,
-    apb2_pre: APBPrescaler::DIV1,
-};
-
-impl Default for Config {
-    #[inline]
-    fn default() -> Config {
-        Config {
-            hse: None,
-            sys: Sysclk::HSI16,
-            mux: None,
-            pll: None,
-            pllsai: None,
-            hsi48: true,
-
-            ls: Default::default(),
-
-            ahb1_pre: AHBPrescaler::DIV1,
-            ahb2_pre: AHBPrescaler::DIV1,
-            ahb3_pre: AHBPrescaler::DIV1,
-            apb1_pre: APBPrescaler::DIV1,
-            apb2_pre: APBPrescaler::DIV1,
-        }
-    }
-}
-
-#[cfg(stm32wb)]
-/// RCC initialization function
-pub(crate) unsafe fn init(config: Config) {
-    let hse_clk = config.hse.as_ref().map(|hse| hse.frequency / hse.prediv);
-
-    let mux_clk = config.mux.as_ref().map(|pll_mux| {
-        (match pll_mux.source {
-            PllSource::HSE => hse_clk.unwrap(),
-            PllSource::HSI16 => HSI_FREQ,
-            _ => unreachable!(),
-        } / pll_mux.prediv)
-    });
-
-    let (pll_r, _pll_q, _pll_p) = match &config.pll {
-        Some(pll) => {
-            let pll_vco = mux_clk.unwrap() * pll.mul as u32;
-
-            (
-                pll.divr.map(|divr| pll_vco / divr),
-                pll.divq.map(|divq| pll_vco / divq),
-                pll.divp.map(|divp| pll_vco / divp),
-            )
-        }
-        None => (None, None, None),
-    };
-
-    let sys_clk = match config.sys {
-        Sysclk::HSE => hse_clk.unwrap(),
-        Sysclk::HSI16 => HSI_FREQ,
-        Sysclk::PLL => pll_r.unwrap(),
-        _ => unreachable!(),
-    };
-
-    let ahb1_clk = sys_clk / config.ahb1_pre;
-    let ahb2_clk = sys_clk / config.ahb2_pre;
-    let ahb3_clk = sys_clk / config.ahb3_pre;
-
-    let (apb1_clk, apb1_tim_clk) = match config.apb1_pre {
-        APBPrescaler::DIV1 => (ahb1_clk, ahb1_clk),
-        pre => {
-            let freq = ahb1_clk / pre;
-            (freq, freq * 2u32)
-        }
-    };
-
-    let (apb2_clk, apb2_tim_clk) = match config.apb2_pre {
-        APBPrescaler::DIV1 => (ahb1_clk, ahb1_clk),
-        pre => {
-            let freq = ahb1_clk / pre;
-            (freq, freq * 2u32)
-        }
-    };
-
-    let rcc = crate::pac::RCC;
-
-    let needs_hsi = if let Some(pll_mux) = &config.mux {
-        pll_mux.source == PllSource::HSI16
-    } else {
-        false
-    };
-
-    if needs_hsi || config.sys == Sysclk::HSI16 {
-        rcc.cr().modify(|w| {
-            w.set_hsion(true);
-        });
-
-        while !rcc.cr().read().hsirdy() {}
-    }
-
-    rcc.cfgr().modify(|w| w.set_stopwuck(true));
-
-    let rtc = config.ls.init();
-
-    match &config.hse {
-        Some(hse) => {
-            rcc.cr().modify(|w| {
-                w.set_hsepre(hse.prediv);
-                w.set_hseon(true);
-            });
-
-            while !rcc.cr().read().hserdy() {}
-        }
-        _ => {}
-    }
-
-    match &config.mux {
-        Some(pll_mux) => {
-            rcc.pllcfgr().modify(|w| {
-                w.set_pllm(pll_mux.prediv);
-                w.set_pllsrc(pll_mux.source.into());
-            });
-        }
-        _ => {}
-    };
-
-    match &config.pll {
-        Some(pll) => {
-            rcc.pllcfgr().modify(|w| {
-                w.set_plln(pll.mul);
-                pll.divp.map(|divp| {
-                    w.set_pllpen(true);
-                    w.set_pllp(divp)
-                });
-                pll.divq.map(|divq| {
-                    w.set_pllqen(true);
-                    w.set_pllq(divq)
-                });
-                pll.divr.map(|divr| {
-                    w.set_pllren(true);
-                    w.set_pllr(divr);
-                });
-            });
-
-            rcc.cr().modify(|w| w.set_pllon(true));
-
-            while !rcc.cr().read().pllrdy() {}
-        }
-        _ => {}
-    }
-
-    let _hsi48 = config.hsi48.then(|| {
-        rcc.crrcr().modify(|w| w.set_hsi48on(true));
-        while !rcc.crrcr().read().hsi48rdy() {}
-
-        Hertz(48_000_000)
-    });
-
-    rcc.cfgr().modify(|w| {
-        w.set_sw(config.sys.into());
-        w.set_hpre(config.ahb1_pre);
-        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre);
-    });
-
-    rcc.extcfgr().modify(|w| {
-        w.set_c2hpre(config.ahb2_pre);
-        w.set_shdhpre(config.ahb3_pre);
-    });
-
-    set_freqs(Clocks {
-        sys: sys_clk,
-        hclk1: ahb1_clk,
-        hclk2: ahb2_clk,
-        hclk3: ahb3_clk,
-        pclk1: apb1_clk,
-        pclk2: apb2_clk,
-        pclk1_tim: apb1_tim_clk,
-        pclk2_tim: apb2_tim_clk,
-        rtc,
-    })
-}

embassy-stm32/src/rcc/wba.rs

@@ -13,20 +13,20 @@ pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
 #[derive(Copy, Clone)]
 pub enum ClockSrc {
     HSE(Hertz),
-    HSI16,
+    HSI,
 }
 
 #[derive(Clone, Copy, Debug)]
 pub enum PllSrc {
     HSE(Hertz),
-    HSI16,
+    HSI,
 }
 
 impl Into<Pllsrc> for PllSrc {
     fn into(self) -> Pllsrc {
         match self {
             PllSrc::HSE(..) => Pllsrc::HSE,
-            PllSrc::HSI16 => Pllsrc::HSI16,
+            PllSrc::HSI => Pllsrc::HSI,
         }
     }
 }
@@ -35,7 +35,7 @@ impl Into<Sw> for ClockSrc {
     fn into(self) -> Sw {
         match self {
             ClockSrc::HSE(..) => Sw::HSE,
-            ClockSrc::HSI16 => Sw::HSI16,
+            ClockSrc::HSI => Sw::HSI,
         }
     }
 }
@@ -52,7 +52,7 @@ pub struct Config {
 impl Default for Config {
     fn default() -> Self {
         Self {
-            mux: ClockSrc::HSI16,
+            mux: ClockSrc::HSI,
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
@@ -70,7 +70,7 @@ pub(crate) unsafe fn init(config: Config) {
 
             freq
         }
-        ClockSrc::HSI16 => {
+        ClockSrc::HSI => {
             RCC.cr().write(|w| w.set_hsion(true));
             while !RCC.cr().read().hsirdy() {}
 

embassy-stm32/src/rcc/wl.rs

@@ -1,184 +0,0 @@
-pub use crate::pac::pwr::vals::Vos as VoltageScale;
-use crate::pac::rcc::vals::Sw;
-pub use crate::pac::rcc::vals::{
-    Adcsel as AdcClockSource, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm, Plln, Pllp, Pllq, Pllr,
-    Pllsrc as PllSource, Ppre as APBPrescaler,
-};
-use crate::pac::{FLASH, RCC};
-use crate::rcc::{set_freqs, Clocks};
-use crate::time::Hertz;
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-
-/// HSE speed
-pub const HSE_FREQ: Hertz = Hertz(32_000_000);
-
-/// System clock mux source
-#[derive(Clone, Copy)]
-pub enum ClockSrc {
-    MSI(MSIRange),
-    HSE,
-    HSI16,
-}
-
-/// Clocks configutation
-pub struct Config {
-    pub mux: ClockSrc,
-    pub ahb_pre: AHBPrescaler,
-    pub shd_ahb_pre: AHBPrescaler,
-    pub apb1_pre: APBPrescaler,
-    pub apb2_pre: APBPrescaler,
-    pub adc_clock_source: AdcClockSource,
-    pub ls: super::LsConfig,
-}
-
-impl Default for Config {
-    #[inline]
-    fn default() -> Config {
-        Config {
-            mux: ClockSrc::MSI(MSIRange::RANGE4M),
-            ahb_pre: AHBPrescaler::DIV1,
-            shd_ahb_pre: AHBPrescaler::DIV1,
-            apb1_pre: APBPrescaler::DIV1,
-            apb2_pre: APBPrescaler::DIV1,
-            adc_clock_source: AdcClockSource::HSI16,
-            ls: Default::default(),
-        }
-    }
-}
-
-pub(crate) unsafe fn init(config: Config) {
-    let (sys_clk, sw, vos) = match config.mux {
-        ClockSrc::HSI16 => (HSI_FREQ, Sw::HSI16, VoltageScale::RANGE2),
-        ClockSrc::HSE => (HSE_FREQ, Sw::HSE, VoltageScale::RANGE1),
-        ClockSrc::MSI(range) => (msirange_to_hertz(range), Sw::MSI, msirange_to_vos(range)),
-    };
-
-    let ahb_freq = sys_clk / config.ahb_pre;
-    let shd_ahb_freq = sys_clk / config.shd_ahb_pre;
-
-    let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let freq = ahb_freq / pre;
-            (freq, freq * 2u32)
-        }
-    };
-
-    let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let freq = ahb_freq / pre;
-            (freq, freq * 2u32)
-        }
-    };
-
-    // Adjust flash latency
-    let flash_clk_src_freq = shd_ahb_freq;
-    let ws = match vos {
-        VoltageScale::RANGE1 => match flash_clk_src_freq.0 {
-            0..=18_000_000 => 0b000,
-            18_000_001..=36_000_000 => 0b001,
-            _ => 0b010,
-        },
-        VoltageScale::RANGE2 => match flash_clk_src_freq.0 {
-            0..=6_000_000 => 0b000,
-            6_000_001..=12_000_000 => 0b001,
-            _ => 0b010,
-        },
-        _ => unreachable!(),
-    };
-
-    FLASH.acr().modify(|w| {
-        w.set_latency(ws);
-    });
-
-    while FLASH.acr().read().latency() != ws {}
-
-    match config.mux {
-        ClockSrc::HSI16 => {
-            // Enable HSI16
-            RCC.cr().write(|w| w.set_hsion(true));
-            while !RCC.cr().read().hsirdy() {}
-        }
-        ClockSrc::HSE => {
-            // Enable HSE
-            RCC.cr().write(|w| {
-                w.set_hsebyppwr(true);
-                w.set_hseon(true);
-            });
-            while !RCC.cr().read().hserdy() {}
-        }
-        ClockSrc::MSI(range) => {
-            let cr = RCC.cr().read();
-            assert!(!cr.msion() || cr.msirdy());
-            RCC.cr().write(|w| {
-                w.set_msirgsel(true);
-                w.set_msirange(range);
-                w.set_msion(true);
-
-                // If LSE is enabled, enable calibration of MSI
-                w.set_msipllen(config.ls.lse.is_some());
-            });
-            while !RCC.cr().read().msirdy() {}
-        }
-    }
-
-    RCC.extcfgr().modify(|w| {
-        w.set_shdhpre(config.shd_ahb_pre);
-    });
-
-    RCC.cfgr().modify(|w| {
-        w.set_sw(sw.into());
-        w.set_hpre(config.ahb_pre);
-        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre);
-    });
-
-    // ADC clock MUX
-    RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source));
-
-    // TODO: switch voltage range
-
-    let rtc = config.ls.init();
-
-    set_freqs(Clocks {
-        sys: sys_clk,
-        hclk1: ahb_freq,
-        hclk2: ahb_freq,
-        hclk3: shd_ahb_freq,
-        pclk1: apb1_freq,
-        pclk2: apb2_freq,
-        pclk3: shd_ahb_freq,
-        pclk1_tim: apb1_tim_freq,
-        pclk2_tim: apb2_tim_freq,
-        rtc,
-    });
-}
-
-fn msirange_to_hertz(range: MSIRange) -> Hertz {
-    match range {
-        MSIRange::RANGE100K => Hertz(100_000),
-        MSIRange::RANGE200K => Hertz(200_000),
-        MSIRange::RANGE400K => Hertz(400_000),
-        MSIRange::RANGE800K => Hertz(800_000),
-        MSIRange::RANGE1M => Hertz(1_000_000),
-        MSIRange::RANGE2M => Hertz(2_000_000),
-        MSIRange::RANGE4M => Hertz(4_000_000),
-        MSIRange::RANGE8M => Hertz(8_000_000),
-        MSIRange::RANGE16M => Hertz(16_000_000),
-        MSIRange::RANGE24M => Hertz(24_000_000),
-        MSIRange::RANGE32M => Hertz(32_000_000),
-        MSIRange::RANGE48M => Hertz(48_000_000),
-        _ => unreachable!(),
-    }
-}
-
-fn msirange_to_vos(range: MSIRange) -> VoltageScale {
-    if range.to_bits() > MSIRange::RANGE16M.to_bits() {
-        VoltageScale::RANGE1
-    } else {
-        VoltageScale::RANGE2
-    }
-}

embassy-stm32/src/rtc/mod.rs

@@ -184,7 +184,11 @@ impl Default for RtcCalibrationCyclePeriod {
 impl Rtc {
     pub fn new(_rtc: impl Peripheral<P = RTC>, rtc_config: RtcConfig) -> Self {
         #[cfg(not(any(stm32l0, stm32f3, stm32l1, stm32f0, stm32f2)))]
-        <RTC as crate::rcc::sealed::RccPeripheral>::enable_and_reset();
+        critical_section::with(|cs| {
+            <RTC as crate::rcc::sealed::RccPeripheral>::enable_and_reset_with_cs(cs);
+            #[cfg(feature = "low-power")]
+            crate::rcc::clock_refcount_sub(cs);
+        });
 
         let mut this = Self {
             #[cfg(feature = "low-power")]

embassy-stm32/src/sdmmc/mod.rs

@@ -1466,7 +1466,7 @@ cfg_if::cfg_if! {
             (SDMMC1) => {
                 critical_section::with(|_| unsafe {
                     let sdmmcsel = crate::pac::RCC.dckcfgr2().read().sdmmc1sel();
-                    if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK {
+                    if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
                         crate::rcc::get_freqs().sys
                     } else {
                         crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC")
@@ -1476,7 +1476,7 @@ cfg_if::cfg_if! {
             (SDMMC2) => {
                 critical_section::with(|_| unsafe {
                     let sdmmcsel = crate::pac::RCC.dckcfgr2().read().sdmmc2sel();
-                    if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK {
+                    if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
                         crate::rcc::get_freqs().sys
                     } else {
                         crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC")

embassy-stm32/src/timer/complementary_pwm.rs

@@ -57,18 +57,20 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
         _ch4: Option<PwmPin<'d, T, Ch4>>,
         _ch4n: Option<ComplementaryPwmPin<'d, T, Ch4>>,
         freq: Hertz,
+        counting_mode: CountingMode,
     ) -> Self {
-        Self::new_inner(tim, freq)
+        Self::new_inner(tim, freq, counting_mode)
     }
 
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz) -> Self {
+    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
         into_ref!(tim);
 
         T::enable_and_reset();
 
         let mut this = Self { inner: tim };
 
-        this.inner.set_frequency(freq);
+        this.inner.set_counting_mode(counting_mode);
+        this.set_freq(freq);
         this.inner.start();
 
         this.inner.enable_outputs();
@@ -95,7 +97,12 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
     }
 
     pub fn set_freq(&mut self, freq: Hertz) {
-        self.inner.set_frequency(freq);
+        let multiplier = if self.inner.get_counting_mode().is_center_aligned() {
+            2u8
+        } else {
+            1u8
+        };
+        self.inner.set_frequency(freq * multiplier);
     }
 
     pub fn get_max_duty(&self) -> u16 {

embassy-stm32/src/timer/mod.rs

@@ -29,10 +29,17 @@ pub(crate) mod sealed {
             Self::regs().cr1().modify(|r| r.set_cen(false));
         }
 
+        /// Reset the counter value to 0
         fn reset(&mut self) {
             Self::regs().cnt().write(|r| r.set_cnt(0));
         }
 
+        /// Set the frequency of how many times per second the timer counts up to the max value or down to 0.
+        ///
+        /// This means that in the default edge-aligned mode,
+        /// the timer counter will wrap around at the same frequency as is being set.
+        /// In center-aligned mode (which not all timers support), the wrap-around frequency is effectively halved
+        /// because it needs to count up and down.
         fn set_frequency(&mut self, frequency: Hertz) {
             let f = frequency.0;
             let timer_f = Self::frequency().0;
@@ -85,8 +92,21 @@ pub(crate) mod sealed {
     pub trait GeneralPurpose16bitInstance: Basic16bitInstance {
         fn regs_gp16() -> crate::pac::timer::TimGp16;
 
-        fn set_count_direction(&mut self, direction: vals::Dir) {
-            Self::regs_gp16().cr1().modify(|r| r.set_dir(direction));
+        fn set_counting_mode(&mut self, mode: CountingMode) {
+            let (cms, dir) = mode.into();
+
+            let timer_enabled = Self::regs().cr1().read().cen();
+            // Changing from edge aligned to center aligned (and vice versa) is not allowed while the timer is running.
+            // Changing direction is discouraged while the timer is running.
+            assert!(!timer_enabled);
+
+            Self::regs_gp16().cr1().modify(|r| r.set_dir(dir));
+            Self::regs_gp16().cr1().modify(|r| r.set_cms(cms))
+        }
+
+        fn get_counting_mode(&self) -> CountingMode {
+            let cr1 = Self::regs_gp16().cr1().read();
+            (cr1.cms(), cr1.dir()).into()
         }
 
         fn set_clock_division(&mut self, ckd: vals::Ckd) {
@@ -293,6 +313,73 @@ impl From<InputTISelection> for stm32_metapac::timer::vals::CcmrInputCcs {
     }
 }
 
+#[repr(u8)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
+pub enum CountingMode {
+    #[default]
+    /// The timer counts up to the reload value and then resets back to 0.
+    EdgeAlignedUp,
+    /// The timer counts down to 0 and then resets back to the reload value.
+    EdgeAlignedDown,
+    /// The timer counts up to the reload value and then counts back to 0.
+    ///
+    /// The output compare interrupt flags of channels configured in output are
+    /// set when the counter is counting down.
+    CenterAlignedDownInterrupts,
+    /// The timer counts up to the reload value and then counts back to 0.
+    ///
+    /// The output compare interrupt flags of channels configured in output are
+    /// set when the counter is counting up.
+    CenterAlignedUpInterrupts,
+    /// The timer counts up to the reload value and then counts back to 0.
+    ///
+    /// The output compare interrupt flags of channels configured in output are
+    /// set when the counter is counting both up or down.
+    CenterAlignedBothInterrupts,
+}
+
+impl CountingMode {
+    pub fn is_edge_aligned(&self) -> bool {
+        match self {
+            CountingMode::EdgeAlignedUp | CountingMode::EdgeAlignedDown => true,
+            _ => false,
+        }
+    }
+
+    pub fn is_center_aligned(&self) -> bool {
+        match self {
+            CountingMode::CenterAlignedDownInterrupts
+            | CountingMode::CenterAlignedUpInterrupts
+            | CountingMode::CenterAlignedBothInterrupts => true,
+            _ => false,
+        }
+    }
+}
+
+impl From<CountingMode> for (vals::Cms, vals::Dir) {
+    fn from(value: CountingMode) -> Self {
+        match value {
+            CountingMode::EdgeAlignedUp => (vals::Cms::EDGEALIGNED, vals::Dir::UP),
+            CountingMode::EdgeAlignedDown => (vals::Cms::EDGEALIGNED, vals::Dir::DOWN),
+            CountingMode::CenterAlignedDownInterrupts => (vals::Cms::CENTERALIGNED1, vals::Dir::UP),
+            CountingMode::CenterAlignedUpInterrupts => (vals::Cms::CENTERALIGNED2, vals::Dir::UP),
+            CountingMode::CenterAlignedBothInterrupts => (vals::Cms::CENTERALIGNED3, vals::Dir::UP),
+        }
+    }
+}
+
+impl From<(vals::Cms, vals::Dir)> for CountingMode {
+    fn from(value: (vals::Cms, vals::Dir)) -> Self {
+        match value {
+            (vals::Cms::EDGEALIGNED, vals::Dir::UP) => CountingMode::EdgeAlignedUp,
+            (vals::Cms::EDGEALIGNED, vals::Dir::DOWN) => CountingMode::EdgeAlignedDown,
+            (vals::Cms::CENTERALIGNED1, _) => CountingMode::CenterAlignedDownInterrupts,
+            (vals::Cms::CENTERALIGNED2, _) => CountingMode::CenterAlignedUpInterrupts,
+            (vals::Cms::CENTERALIGNED3, _) => CountingMode::CenterAlignedBothInterrupts,
+        }
+    }
+}
+
 #[derive(Clone, Copy)]
 pub enum OutputCompareMode {
     Frozen,
@@ -471,9 +558,5 @@ foreach_interrupt! {
                 crate::pac::$inst
             }
         }
-
-
-
-
     };
 }

embassy-stm32/src/timer/simple_pwm.rs

@@ -56,18 +56,20 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
         _ch3: Option<PwmPin<'d, T, Ch3>>,
         _ch4: Option<PwmPin<'d, T, Ch4>>,
         freq: Hertz,
+        counting_mode: CountingMode,
     ) -> Self {
-        Self::new_inner(tim, freq)
+        Self::new_inner(tim, freq, counting_mode)
     }
 
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz) -> Self {
+    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
         into_ref!(tim);
 
         T::enable_and_reset();
 
         let mut this = Self { inner: tim };
 
-        this.inner.set_frequency(freq);
+        this.inner.set_counting_mode(counting_mode);
+        this.set_freq(freq);
         this.inner.start();
 
         this.inner.enable_outputs();
@@ -92,7 +94,12 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
     }
 
     pub fn set_freq(&mut self, freq: Hertz) {
-        self.inner.set_frequency(freq);
+        let multiplier = if self.inner.get_counting_mode().is_center_aligned() {
+            2u8
+        } else {
+            1u8
+        };
+        self.inner.set_frequency(freq * multiplier);
     }
 
     pub fn get_max_duty(&self) -> u16 {

examples/stm32f4/src/bin/eth.rs

@@ -10,7 +10,7 @@ use embassy_stm32::eth::generic_smi::GenericSMI;
 use embassy_stm32::eth::{Ethernet, PacketQueue};
 use embassy_stm32::peripherals::ETH;
 use embassy_stm32::rng::Rng;
-use embassy_stm32::time::mhz;
+use embassy_stm32::time::Hertz;
 use embassy_stm32::{bind_interrupts, eth, peripherals, rng, Config};
 use embassy_time::Timer;
 use embedded_io_async::Write;
@@ -32,7 +32,25 @@ async fn net_task(stack: &'static Stack<Device>) -> ! {
 #[embassy_executor::main]
 async fn main(spawner: Spawner) -> ! {
     let mut config = Config::default();
-    config.rcc.sys_ck = Some(mhz(200));
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL180,
+            divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
+            divq: None,
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
+    }
     let p = embassy_stm32::init(config);
 
     info!("Hello World!");

examples/stm32f4/src/bin/hello.rs

@@ -4,15 +4,13 @@
 
 use defmt::info;
 use embassy_executor::Spawner;
-use embassy_stm32::time::Hertz;
 use embassy_stm32::Config;
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) -> ! {
-    let mut config = Config::default();
-    config.rcc.sys_ck = Some(Hertz(84_000_000));
+    let config = Config::default();
     let _p = embassy_stm32::init(config);
 
     loop {

examples/stm32f4/src/bin/pwm.rs

@@ -17,7 +17,7 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     let ch1 = PwmPin::new_ch1(p.PE9, OutputType::PushPull);
-    let mut pwm = SimplePwm::new(p.TIM1, Some(ch1), None, None, None, khz(10));
+    let mut pwm = SimplePwm::new(p.TIM1, Some(ch1), None, None, None, khz(10), Default::default());
     let max = pwm.get_max_duty();
     pwm.enable(Channel::Ch1);
 

examples/stm32f4/src/bin/pwm_complementary.rs

@@ -30,6 +30,7 @@ async fn main(_spawner: Spawner) {
         None,
         None,
         khz(10),
+        Default::default(),
     );
 
     let max = pwm.get_max_duty();

examples/stm32f4/src/bin/sdmmc.rs

@@ -5,7 +5,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::sdmmc::{DataBlock, Sdmmc};
-use embassy_stm32::time::mhz;
+use embassy_stm32::time::{mhz, Hertz};
 use embassy_stm32::{bind_interrupts, peripherals, sdmmc, Config};
 use {defmt_rtt as _, panic_probe as _};
 
@@ -20,8 +20,25 @@ bind_interrupts!(struct Irqs {
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.sys_ck = Some(mhz(48));
-    config.rcc.pll48 = true;
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL168,
+            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
+    }
     let p = embassy_stm32::init(config);
     info!("Hello World!");
 

examples/stm32f4/src/bin/usb_ethernet.rs

@@ -7,7 +7,7 @@ use embassy_executor::Spawner;
 use embassy_net::tcp::TcpSocket;
 use embassy_net::{Stack, StackResources};
 use embassy_stm32::rng::{self, Rng};
-use embassy_stm32::time::mhz;
+use embassy_stm32::time::Hertz;
 use embassy_stm32::usb_otg::Driver;
 use embassy_stm32::{bind_interrupts, peripherals, usb_otg, Config};
 use embassy_usb::class::cdc_ncm::embassy_net::{Device, Runner, State as NetState};
@@ -46,9 +46,25 @@ async fn main(spawner: Spawner) {
     info!("Hello World!");
 
     let mut config = Config::default();
-    config.rcc.pll48 = true;
-    config.rcc.sys_ck = Some(mhz(48));
-
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL168,
+            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
+    }
     let p = embassy_stm32::init(config);
 
     // Create the driver, from the HAL.

examples/stm32f4/src/bin/usb_serial.rs

@@ -4,7 +4,7 @@
 
 use defmt::{panic, *};
 use embassy_executor::Spawner;
-use embassy_stm32::time::mhz;
+use embassy_stm32::time::Hertz;
 use embassy_stm32::usb_otg::{Driver, Instance};
 use embassy_stm32::{bind_interrupts, peripherals, usb_otg, Config};
 use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
@@ -22,9 +22,25 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     let mut config = Config::default();
-    config.rcc.pll48 = true;
-    config.rcc.sys_ck = Some(mhz(48));
-
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL168,
+            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
+    }
     let p = embassy_stm32::init(config);
 
     // Create the driver, from the HAL.

examples/stm32f7/src/bin/eth.rs

@@ -10,7 +10,7 @@ use embassy_stm32::eth::generic_smi::GenericSMI;
 use embassy_stm32::eth::{Ethernet, PacketQueue};
 use embassy_stm32::peripherals::ETH;
 use embassy_stm32::rng::Rng;
-use embassy_stm32::time::mhz;
+use embassy_stm32::time::Hertz;
 use embassy_stm32::{bind_interrupts, eth, peripherals, rng, Config};
 use embassy_time::Timer;
 use embedded_io_async::Write;
@@ -33,7 +33,25 @@ async fn net_task(stack: &'static Stack<Device>) -> ! {
 #[embassy_executor::main]
 async fn main(spawner: Spawner) -> ! {
     let mut config = Config::default();
-    config.rcc.sys_ck = Some(mhz(200));
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL216,
+            divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
+            divq: None,
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
+    }
     let p = embassy_stm32::init(config);
 
     info!("Hello World!");

examples/stm32f7/src/bin/hello.rs

@@ -4,15 +4,13 @@
 
 use defmt::info;
 use embassy_executor::Spawner;
-use embassy_stm32::time::Hertz;
 use embassy_stm32::Config;
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) -> ! {
-    let mut config = Config::default();
-    config.rcc.sys_ck = Some(Hertz(84_000_000));
+    let config = Config::default();
     let _p = embassy_stm32::init(config);
 
     loop {

examples/stm32f7/src/bin/sdmmc.rs

@@ -5,7 +5,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::sdmmc::Sdmmc;
-use embassy_stm32::time::mhz;
+use embassy_stm32::time::{mhz, Hertz};
 use embassy_stm32::{bind_interrupts, peripherals, sdmmc, Config};
 use {defmt_rtt as _, panic_probe as _};
 
@@ -16,8 +16,25 @@ bind_interrupts!(struct Irqs {
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.sys_ck = Some(mhz(200));
-    config.rcc.pll48 = true;
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL216,
+            divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
+            divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
+    }
     let p = embassy_stm32::init(config);
 
     info!("Hello World!");

examples/stm32f7/src/bin/usb_serial.rs

@@ -4,7 +4,7 @@
 
 use defmt::{panic, *};
 use embassy_executor::Spawner;
-use embassy_stm32::time::mhz;
+use embassy_stm32::time::Hertz;
 use embassy_stm32::usb_otg::{Driver, Instance};
 use embassy_stm32::{bind_interrupts, peripherals, usb_otg, Config};
 use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
@@ -22,10 +22,25 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     let mut config = Config::default();
-    config.rcc.hse = Some(mhz(8));
-    config.rcc.pll48 = true;
-    config.rcc.sys_ck = Some(mhz(200));
-
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL216,
+            divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
+            divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
+    }
     let p = embassy_stm32::init(config);
 
     // Create the driver, from the HAL.

examples/stm32g4/src/bin/adc.rs

@@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
 
     config.rcc.pll = Some(Pll {
-        source: PllSrc::HSI16,
+        source: PllSrc::HSI,
         prediv_m: PllM::DIV4,
         mul_n: PllN::MUL85,
         div_p: None,

examples/stm32g4/src/bin/pll.rs

@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
 
     config.rcc.pll = Some(Pll {
-        source: PllSrc::HSI16,
+        source: PllSrc::HSI,
         prediv_m: PllM::DIV4,
         mul_n: PllN::MUL85,
         div_p: None,

examples/stm32g4/src/bin/pwm.rs

@@ -17,7 +17,7 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     let ch1 = PwmPin::new_ch1(p.PC0, OutputType::PushPull);
-    let mut pwm = SimplePwm::new(p.TIM1, Some(ch1), None, None, None, khz(10));
+    let mut pwm = SimplePwm::new(p.TIM1, Some(ch1), None, None, None, khz(10), Default::default());
     let max = pwm.get_max_duty();
     pwm.enable(Channel::Ch1);
 

examples/stm32h5/src/bin/eth.rs

@@ -43,7 +43,7 @@ async fn main(spawner: Spawner) -> ! {
         mode: HseMode::BypassDigital,
     });
     config.rcc.pll1 = Some(Pll {
-        source: PllSource::Hse,
+        source: PllSource::HSE,
         prediv: PllPreDiv::DIV2,
         mul: PllMul::MUL125,
         divp: Some(PllDiv::DIV2),
@@ -54,7 +54,7 @@ async fn main(spawner: Spawner) -> ! {
     config.rcc.apb1_pre = APBPrescaler::DIV1;
     config.rcc.apb2_pre = APBPrescaler::DIV1;
     config.rcc.apb3_pre = APBPrescaler::DIV1;
-    config.rcc.sys = Sysclk::Pll1P;
+    config.rcc.sys = Sysclk::PLL1_P;
     config.rcc.voltage_scale = VoltageScale::Scale0;
     let p = embassy_stm32::init(config);
     info!("Hello World!");

examples/stm32h5/src/bin/usb_serial.rs

@@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) {
         mode: HseMode::BypassDigital,
     });
     config.rcc.pll1 = Some(Pll {
-        source: PllSource::Hse,
+        source: PllSource::HSE,
         prediv: PllPreDiv::DIV2,
         mul: PllMul::MUL125,
         divp: Some(PllDiv::DIV2), // 250mhz
@@ -41,7 +41,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.apb1_pre = APBPrescaler::DIV4;
     config.rcc.apb2_pre = APBPrescaler::DIV2;
     config.rcc.apb3_pre = APBPrescaler::DIV4;
-    config.rcc.sys = Sysclk::Pll1P;
+    config.rcc.sys = Sysclk::PLL1_P;
     config.rcc.voltage_scale = VoltageScale::Scale0;
     let p = embassy_stm32::init(config);
 

examples/stm32h7/src/bin/adc.rs

@@ -14,10 +14,10 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
@@ -25,13 +25,14 @@ async fn main(_spawner: Spawner) {
             divr: None,
         });
         config.rcc.pll2 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV8), // 100mhz
             divq: None,
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/camera.rs

@@ -28,17 +28,17 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
             divq: Some(PllDiv::DIV8), // 100mhz
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/dac.rs

@@ -16,10 +16,10 @@ fn main() -> ! {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
@@ -27,13 +27,14 @@ fn main() -> ! {
             divr: None,
         });
         config.rcc.pll2 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV8), // 100mhz
             divq: None,
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/dac_dma.rs

@@ -24,10 +24,10 @@ async fn main(spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
@@ -35,13 +35,14 @@ async fn main(spawner: Spawner) {
             divr: None,
         });
         config.rcc.pll2 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV8), // 100mhz
             divq: None,
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/eth.rs

@@ -34,18 +34,18 @@ async fn main(spawner: Spawner) -> ! {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
         config.rcc.hsi48 = true; // needed for RNG
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
             divq: None,
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/eth_client.rs

@@ -35,18 +35,18 @@ async fn main(spawner: Spawner) -> ! {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
         config.rcc.hsi48 = true; // needed for RNG
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
             divq: None,
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/fmc.rs

@@ -14,17 +14,17 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
             divq: Some(PllDiv::DIV8), // 100mhz
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/low_level_timer_api.rs

@@ -17,18 +17,18 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
         config.rcc.hsi48 = true; // needed for RNG
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
             divq: Some(PllDiv::DIV8), // 100mhz
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/pwm.rs

@@ -17,17 +17,17 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
             divq: None,
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
@@ -39,7 +39,7 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     let ch1 = PwmPin::new_ch1(p.PA6, OutputType::PushPull);
-    let mut pwm = SimplePwm::new(p.TIM3, Some(ch1), None, None, None, khz(10));
+    let mut pwm = SimplePwm::new(p.TIM3, Some(ch1), None, None, None, khz(10), Default::default());
     let max = pwm.get_max_duty();
     pwm.enable(Channel::Ch1);
 

examples/stm32h7/src/bin/sdmmc.rs

@@ -18,17 +18,17 @@ async fn main(_spawner: Spawner) -> ! {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
             divq: Some(PllDiv::DIV4), // default clock chosen by SDMMCSEL. 200 Mhz
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/spi.rs

@@ -40,17 +40,17 @@ fn main() -> ! {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
             divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/spi_dma.rs

@@ -36,17 +36,17 @@ fn main() -> ! {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
             divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32h7/src/bin/usb_serial.rs

@@ -23,18 +23,18 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
         config.rcc.hsi48 = true; // needed for USB
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
             divq: None,
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz

examples/stm32l0/src/bin/lora_cad.rs

@@ -23,7 +23,7 @@ const LORA_FREQUENCY_IN_HZ: u32 = 903_900_000; // warning: set this appropriatel
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
-    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSI16;
+    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSI;
     config.rcc.enable_hsi48 = true;
     let p = embassy_stm32::init(config);
 

examples/stm32l0/src/bin/lora_lorawan.rs

@@ -33,7 +33,7 @@ const LORAWAN_REGION: region::Region = region::Region::EU868; // warning: set th
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
-    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSI16;
+    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSI;
     config.rcc.enable_hsi48 = true;
     let p = embassy_stm32::init(config);
 

examples/stm32l0/src/bin/lora_p2p_receive.rs

@@ -23,7 +23,7 @@ const LORA_FREQUENCY_IN_HZ: u32 = 903_900_000; // warning: set this appropriatel
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
-    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSI16;
+    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSI;
     config.rcc.enable_hsi48 = true;
     let p = embassy_stm32::init(config);
 

examples/stm32l0/src/bin/lora_p2p_send.rs

@@ -23,7 +23,7 @@ const LORA_FREQUENCY_IN_HZ: u32 = 903_900_000; // warning: set this appropriatel
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
-    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSI16;
+    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSI;
     config.rcc.enable_hsi48 = true;
     let p = embassy_stm32::init(config);
 

examples/stm32l4/src/bin/rng.rs

@@ -16,8 +16,8 @@ bind_interrupts!(struct Irqs {
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.mux = ClockSrc::PLL;
-    config.rcc.hsi16 = true;
+    config.rcc.mux = ClockSrc::PLL1_R;
+    config.rcc.hsi = true;
     config.rcc.pll = Some(Pll {
         source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,

examples/stm32l4/src/bin/rtc.rs

@@ -5,7 +5,6 @@
 use chrono::{NaiveDate, NaiveDateTime};
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, LsConfig, PLLSource, Pll, PllMul, PllPreDiv, PllRDiv};
 use embassy_stm32::rtc::{Rtc, RtcConfig};
 use embassy_stm32::time::Hertz;
 use embassy_stm32::Config;
@@ -15,17 +14,23 @@ use {defmt_rtt as _, panic_probe as _};
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.mux = ClockSrc::PLL;
-    config.rcc.hse = Some(Hertz::mhz(8));
-    config.rcc.pll = Some(Pll {
-        source: PLLSource::HSE,
-        prediv: PllPreDiv::DIV1,
-        mul: PllMul::MUL20,
-        divp: None,
-        divq: None,
-        divr: Some(PllRDiv::DIV2), // sysclk 80Mhz clock (8 / 1 * 20 / 2)
-    });
-    config.rcc.ls = LsConfig::default_lse();
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz::mhz(8),
+            mode: HseMode::Oscillator,
+        });
+        config.rcc.pll = Some(Pll {
+            source: PLLSource::HSE,
+            prediv: PllPreDiv::DIV1,
+            mul: PllMul::MUL20,
+            divp: None,
+            divq: None,
+            divr: Some(PllRDiv::DIV2), // sysclk 80Mhz clock (8 / 1 * 20 / 2)
+        });
+        config.rcc.ls = LsConfig::default_lse();
+    }
     let p = embassy_stm32::init(config);
 
     info!("Hello World!");

examples/stm32l4/src/bin/spe_adin1110_http_server.rs

@@ -48,7 +48,6 @@ use embassy_net_adin1110::{self, Device, Runner, ADIN1110};
 use embedded_hal_bus::spi::ExclusiveDevice;
 use hal::gpio::Pull;
 use hal::i2c::Config as I2C_Config;
-use hal::rcc::{ClockSrc, PLLSource, Pll, PllMul, PllPreDiv, PllRDiv};
 use hal::spi::{Config as SPI_Config, Spi};
 use hal::time::Hertz;
 
@@ -74,20 +73,25 @@ async fn main(spawner: Spawner) {
     defmt::println!("Start main()");
 
     let mut config = embassy_stm32::Config::default();
-
-    // 80Mhz clock (Source: 8 / SrcDiv: 1 * PLLMul 20 / ClkDiv 2)
-    // 80MHz highest frequency for flash 0 wait.
-    config.rcc.mux = ClockSrc::PLL;
-    config.rcc.hse = Some(Hertz::mhz(8));
-    config.rcc.pll = Some(Pll {
-        source: PLLSource::HSE,
-        prediv: PllPreDiv::DIV1,
-        mul: PllMul::MUL20,
-        divp: None,
-        divq: None,
-        divr: Some(PllRDiv::DIV2), // sysclk 80Mhz clock (8 / 1 * 20 / 2)
-    });
-    config.rcc.hsi48 = true; // needed for rng
+    {
+        use embassy_stm32::rcc::*;
+        // 80Mhz clock (Source: 8 / SrcDiv: 1 * PLLMul 20 / ClkDiv 2)
+        // 80MHz highest frequency for flash 0 wait.
+        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz::mhz(8),
+            mode: HseMode::Oscillator,
+        });
+        config.rcc.pll = Some(Pll {
+            source: PLLSource::HSE,
+            prediv: PllPreDiv::DIV1,
+            mul: PllMul::MUL20,
+            divp: None,
+            divq: None,
+            divr: Some(PllRDiv::DIV2), // sysclk 80Mhz clock (8 / 1 * 20 / 2)
+        });
+        config.rcc.hsi48 = true; // needed for rng
+    }
 
     let dp = embassy_stm32::init(config);
 

examples/stm32l4/src/bin/usb_serial.rs

@@ -24,8 +24,8 @@ async fn main(_spawner: Spawner) {
 
     let mut config = Config::default();
     config.rcc.hsi48 = true;
-    config.rcc.mux = ClockSrc::PLL;
-    config.rcc.hsi16 = true;
+    config.rcc.mux = ClockSrc::PLL1_R;
+    config.rcc.hsi = true;
     config.rcc.pll = Some(Pll {
         source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,

examples/stm32l5/src/bin/rng.rs

@@ -16,11 +16,11 @@ bind_interrupts!(struct Irqs {
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.hsi16 = true;
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.hsi = true;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 64Mhz clock (16 / 1 * 8 / 2)
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL8,
         divp: None,

examples/stm32l5/src/bin/usb_ethernet.rs

@@ -45,11 +45,11 @@ async fn net_task(stack: &'static Stack<Device<'static, MTU>>) -> ! {
 #[embassy_executor::main]
 async fn main(spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.hsi16 = true;
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.hsi = true;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,

examples/stm32l5/src/bin/usb_hid_mouse.rs

@@ -22,11 +22,11 @@ bind_interrupts!(struct Irqs {
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.hsi16 = true;
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.hsi = true;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,

examples/stm32l5/src/bin/usb_serial.rs

@@ -20,11 +20,11 @@ bind_interrupts!(struct Irqs {
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.hsi16 = true;
-    config.rcc.mux = ClockSrc::PLL;
+    config.rcc.hsi = true;
+    config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
-        source: PLLSource::HSI16,
+        source: PLLSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,

examples/stm32u5/src/bin/usb_serial.rs

@@ -23,8 +23,8 @@ async fn main(_spawner: Spawner) {
     info!("Hello World!");
 
     let mut config = Config::default();
-    config.rcc.mux = ClockSrc::PLL1R(PllConfig {
-        source: PllSrc::HSI16,
+    config.rcc.mux = ClockSrc::PLL1_R(PllConfig {
+        source: PllSrc::HSI,
         m: Pllm::DIV2,
         n: Plln::MUL10,
         r: Plldiv::DIV1,

examples/stm32wl/src/bin/lora_lorawan.rs

@@ -12,7 +12,8 @@ use embassy_lora::LoraTimer;
 use embassy_stm32::gpio::{Level, Output, Pin, Speed};
 use embassy_stm32::rng::{self, Rng};
 use embassy_stm32::spi::Spi;
-use embassy_stm32::{bind_interrupts, pac, peripherals};
+use embassy_stm32::time::Hertz;
+use embassy_stm32::{bind_interrupts, peripherals};
 use embassy_time::Delay;
 use lora_phy::mod_params::*;
 use lora_phy::sx1261_2::SX1261_2;
@@ -33,11 +34,25 @@ bind_interrupts!(struct Irqs{
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
-    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE;
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(32_000_000),
+            mode: HseMode::Bypass,
+            prescaler: HsePrescaler::DIV1,
+        });
+        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.pll = Some(Pll {
+            source: PLLSource::HSE,
+            prediv: PllPreDiv::DIV2,
+            mul: PllMul::MUL6,
+            divp: None,
+            divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG
+            divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2)
+        });
+    }
     let p = embassy_stm32::init(config);
 
-    pac::RCC.ccipr().modify(|w| w.set_rngsel(0b01));
-
     let spi = Spi::new_subghz(p.SUBGHZSPI, p.DMA1_CH1, p.DMA1_CH2);
 
     // Set CTRL1 and CTRL3 for high-power transmission, while CTRL2 acts as an RF switch between tx and rx

examples/stm32wl/src/bin/lora_p2p_receive.rs

@@ -11,6 +11,7 @@ use embassy_lora::iv::{InterruptHandler, Stm32wlInterfaceVariant};
 use embassy_stm32::bind_interrupts;
 use embassy_stm32::gpio::{Level, Output, Pin, Speed};
 use embassy_stm32::spi::Spi;
+use embassy_stm32::time::Hertz;
 use embassy_time::{Delay, Timer};
 use lora_phy::mod_params::*;
 use lora_phy::sx1261_2::SX1261_2;
@@ -26,7 +27,23 @@ bind_interrupts!(struct Irqs{
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
-    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE;
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(32_000_000),
+            mode: HseMode::Bypass,
+            prescaler: HsePrescaler::DIV1,
+        });
+        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.pll = Some(Pll {
+            source: PLLSource::HSE,
+            prediv: PllPreDiv::DIV2,
+            mul: PllMul::MUL6,
+            divp: None,
+            divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG
+            divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2)
+        });
+    }
     let p = embassy_stm32::init(config);
 
     let spi = Spi::new_subghz(p.SUBGHZSPI, p.DMA1_CH1, p.DMA1_CH2);

examples/stm32wl/src/bin/lora_p2p_send.rs

@@ -11,6 +11,7 @@ use embassy_lora::iv::{InterruptHandler, Stm32wlInterfaceVariant};
 use embassy_stm32::bind_interrupts;
 use embassy_stm32::gpio::{Level, Output, Pin, Speed};
 use embassy_stm32::spi::Spi;
+use embassy_stm32::time::Hertz;
 use embassy_time::Delay;
 use lora_phy::mod_params::*;
 use lora_phy::sx1261_2::SX1261_2;
@@ -26,7 +27,23 @@ bind_interrupts!(struct Irqs{
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
-    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE;
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(32_000_000),
+            mode: HseMode::Bypass,
+            prescaler: HsePrescaler::DIV1,
+        });
+        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.pll = Some(Pll {
+            source: PLLSource::HSE,
+            prediv: PllPreDiv::DIV2,
+            mul: PllMul::MUL6,
+            divp: None,
+            divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG
+            divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2)
+        });
+    }
     let p = embassy_stm32::init(config);
 
     let spi = Spi::new_subghz(p.SUBGHZSPI, p.DMA1_CH1, p.DMA1_CH2);

examples/stm32wl/src/bin/random.rs

@@ -5,7 +5,8 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::rng::{self, Rng};
-use embassy_stm32::{bind_interrupts, pac, peripherals};
+use embassy_stm32::time::Hertz;
+use embassy_stm32::{bind_interrupts, peripherals};
 use {defmt_rtt as _, panic_probe as _};
 
 bind_interrupts!(struct Irqs{
@@ -15,12 +16,24 @@ bind_interrupts!(struct Irqs{
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
-    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE;
-
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(32_000_000),
+            mode: HseMode::Bypass,
+            prescaler: HsePrescaler::DIV1,
+        });
+        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.pll = Some(Pll {
+            source: PLLSource::HSE,
+            prediv: PllPreDiv::DIV2,
+            mul: PllMul::MUL6,
+            divp: None,
+            divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG
+            divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2)
+        });
+    }
     let p = embassy_stm32::init(config);
-    pac::RCC.ccipr().modify(|w| {
-        w.set_rngsel(0b01);
-    });
 
     info!("Hello World!");
 

examples/stm32wl/src/bin/rtc.rs

@@ -5,20 +5,34 @@
 use chrono::{NaiveDate, NaiveDateTime};
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, LsConfig};
 use embassy_stm32::rtc::{Rtc, RtcConfig};
+use embassy_stm32::time::Hertz;
 use embassy_stm32::Config;
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
 
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
-    let p = {
-        let mut config = Config::default();
-        config.rcc.mux = ClockSrc::HSE;
+    let mut config = Config::default();
+    {
+        use embassy_stm32::rcc::*;
         config.rcc.ls = LsConfig::default_lse();
-        embassy_stm32::init(config)
-    };
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(32_000_000),
+            mode: HseMode::Bypass,
+            prescaler: HsePrescaler::DIV1,
+        });
+        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.pll = Some(Pll {
+            source: PLLSource::HSE,
+            prediv: PllPreDiv::DIV2,
+            mul: PllMul::MUL6,
+            divp: None,
+            divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG
+            divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2)
+        });
+    }
+    let p = embassy_stm32::init(config);
     info!("Hello World!");
 
     let now = NaiveDate::from_ymd_opt(2020, 5, 15)

tests/rp/src/bin/adc.rs

@@ -93,6 +93,7 @@ async fn main(_spawner: Spawner) {
         adc.read_many(
             &mut Channel::new_pin(&mut p.PIN_29, Pull::Down),
             &mut low,
+            1,
             &mut p.DMA_CH0,
         )
         .await
@@ -100,12 +101,18 @@ async fn main(_spawner: Spawner) {
         adc.read_many(
             &mut Channel::new_pin(&mut p.PIN_29, Pull::None),
             &mut none,
+            1,
             &mut p.DMA_CH0,
         )
         .await
         .unwrap();
-        adc.read_many_raw(&mut Channel::new_pin(&mut p.PIN_29, Pull::Up), &mut up, &mut p.DMA_CH0)
-            .await;
+        adc.read_many_raw(
+            &mut Channel::new_pin(&mut p.PIN_29, Pull::Up),
+            &mut up,
+            1,
+            &mut p.DMA_CH0,
+        )
+        .await;
         defmt::assert!(low.iter().zip(none.iter()).all(|(l, n)| *l >> 4 < *n as u16));
         defmt::assert!(up.iter().all(|s| s.good()));
         defmt::assert!(none.iter().zip(up.iter()).all(|(n, u)| (*n as u16) < u.value()));
@@ -115,6 +122,7 @@ async fn main(_spawner: Spawner) {
         adc.read_many(
             &mut Channel::new_temp_sensor(&mut p.ADC_TEMP_SENSOR),
             &mut temp,
+            1,
             &mut p.DMA_CH0,
         )
         .await

tests/stm32/Cargo.toml

@@ -12,9 +12,13 @@ stm32g071rb = ["embassy-stm32/stm32g071rb", "not-gpdma", "dac-adc-pin"]
 stm32c031c6 = ["embassy-stm32/stm32c031c6", "not-gpdma"]
 stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "not-gpdma", "rng"]
 stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac-adc-pin", "rng"]
+stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng"]
+stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng"]
 stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
 stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng"]
 stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng"]
+stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng"]
+stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng"]
 stm32l073rz = ["embassy-stm32/stm32l073rz", "not-gpdma", "rng"]
 stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"]
 stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng"]
@@ -24,6 +28,7 @@ stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
 stm32f207zg = ["embassy-stm32/stm32f207zg", "chrono", "not-gpdma", "eth", "rng"]
 stm32f303ze = ["embassy-stm32/stm32f303ze", "chrono", "not-gpdma"]
 stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma", "rng"]
+stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
 
 eth = []
 rng = []

tests/stm32/build.rs

@@ -8,12 +8,14 @@ fn main() -> Result<(), Box<dyn Error>> {
     println!("cargo:rustc-link-search={}", out.display());
     println!("cargo:rustc-link-arg-bins=--nmagic");
 
-    // too little RAM to run from RAM.
     if cfg!(any(
+        // too little RAM to run from RAM.
         feature = "stm32f103c8",
         feature = "stm32c031c6",
         feature = "stm32wb55rg",
         feature = "stm32l073rz",
+        // wrong ram size in stm32-data
+        feature = "stm32wl55jc",
     )) {
         println!("cargo:rustc-link-arg-bins=-Tlink.x");
         println!("cargo:rerun-if-changed=link.x");

tests/stm32/src/bin/eth.rs

@@ -60,6 +60,8 @@ async fn main(spawner: Spawner) {
     let n = 4;
     #[cfg(feature = "stm32f207zg")]
     let n = 5;
+    #[cfg(feature = "stm32h753zi")]
+    let n = 6;
 
     let mac_addr = [0x00, n, 0xDE, 0xAD, 0xBE, 0xEF];
 

tests/stm32/src/bin/gpio.rs

@@ -217,8 +217,7 @@ async fn main(_spawner: Spawner) {
 }
 
 fn delay() {
-    #[cfg(feature = "stm32h755zi")]
-    cortex_m::asm::delay(10000);
-    #[cfg(not(feature = "stm32h755zi"))]
+    #[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi", feature = "stm32h7a3zi"))]
+    cortex_m::asm::delay(9000);
     cortex_m::asm::delay(1000);
 }

tests/stm32/src/bin/rng.rs

@@ -11,7 +11,12 @@ use embassy_stm32::rng::Rng;
 use embassy_stm32::{bind_interrupts, peripherals, rng};
 use {defmt_rtt as _, panic_probe as _};
 
-#[cfg(any(feature = "stm32l4a6zg", feature = "stm32h755zi", feature = "stm32f429zi"))]
+#[cfg(any(
+    feature = "stm32l4a6zg",
+    feature = "stm32h755zi",
+    feature = "stm32h753zi",
+    feature = "stm32f429zi"
+))]
 bind_interrupts!(struct Irqs {
    HASH_RNG => rng::InterruptHandler<peripherals::RNG>;
 });
@@ -23,6 +28,7 @@ bind_interrupts!(struct Irqs {
     feature = "stm32l4a6zg",
     feature = "stm32l073rz",
     feature = "stm32h755zi",
+    feature = "stm32h753zi",
     feature = "stm32f429zi"
 )))]
 bind_interrupts!(struct Irqs {

tests/stm32/src/bin/stop.rs

@@ -11,7 +11,7 @@ use common::*;
 use cortex_m_rt::entry;
 use embassy_executor::Spawner;
 use embassy_stm32::low_power::{stop_with_rtc, Executor};
-use embassy_stm32::rcc::LsConfig;
+use embassy_stm32::rcc::{low_power_ready, LsConfig};
 use embassy_stm32::rtc::{Rtc, RtcConfig};
 use embassy_stm32::Config;
 use embassy_time::Timer;
@@ -28,6 +28,7 @@ fn main() -> ! {
 async fn task_1() {
     for _ in 0..9 {
         info!("task 1: waiting for 500ms...");
+        defmt::assert!(low_power_ready());
         Timer::after_millis(500).await;
     }
 }
@@ -36,6 +37,7 @@ async fn task_1() {
 async fn task_2() {
     for _ in 0..5 {
         info!("task 2: waiting for 1000ms...");
+        defmt::assert!(low_power_ready());
         Timer::after_millis(1000).await;
     }
 

tests/stm32/src/common.rs

@@ -18,8 +18,14 @@ teleprobe_meta::target!(b"nucleo-stm32f429zi");
 teleprobe_meta::target!(b"nucleo-stm32wb55rg");
 #[cfg(feature = "stm32h755zi")]
 teleprobe_meta::target!(b"nucleo-stm32h755zi");
+#[cfg(feature = "stm32h753zi")]
+teleprobe_meta::target!(b"nucleo-stm32h753zi");
+#[cfg(feature = "stm32h7a3zi")]
+teleprobe_meta::target!(b"nucleo-stm32h7a3zi");
 #[cfg(feature = "stm32u585ai")]
 teleprobe_meta::target!(b"iot-stm32u585ai");
+#[cfg(feature = "stm32u5a5zj")]
+teleprobe_meta::target!(b"nucleo-stm32u5a5zj");
 #[cfg(feature = "stm32h563zi")]
 teleprobe_meta::target!(b"nucleo-stm32h563zi");
 #[cfg(feature = "stm32c031c6")]
@@ -42,6 +48,10 @@ teleprobe_meta::target!(b"nucleo-stm32f207zg");
 teleprobe_meta::target!(b"nucleo-stm32f303ze");
 #[cfg(feature = "stm32l496zg")]
 teleprobe_meta::target!(b"nucleo-stm32l496zg");
+#[cfg(feature = "stm32wl55jc")]
+teleprobe_meta::target!(b"nucleo-stm32wl55jc");
+#[cfg(feature = "stm32wba52cg")]
+teleprobe_meta::target!(b"nucleo-stm32wba52cg");
 
 macro_rules! define_peris {
     ($($name:ident = $peri:ident,)* $(@irq $irq_name:ident = $irq_code:tt,)*) => {
@@ -103,18 +113,30 @@ define_peris!(
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
     @irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
 );
-#[cfg(feature = "stm32h755zi")]
+#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
 define_peris!(
     UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
     @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
 );
+#[cfg(feature = "stm32h7a3zi")]
+define_peris!(
+    UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
+    SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
+    @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
+);
 #[cfg(feature = "stm32u585ai")]
 define_peris!(
     UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
     SPI = SPI1, SPI_SCK = PE13, SPI_MOSI = PE15, SPI_MISO = PE14, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
     @irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
 );
+#[cfg(feature = "stm32u5a5zj")]
+define_peris!(
+    UART = LPUART1, UART_TX = PG7, UART_RX = PG8, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
+    SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
+    @irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
+);
 #[cfg(feature = "stm32h563zi")]
 define_peris!(
     UART = LPUART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
@@ -181,11 +203,35 @@ define_peris!(
     SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
     @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
 );
+#[cfg(feature = "stm32wl55jc")]
+define_peris!(
+    UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
+    SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
+    @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
+);
+#[cfg(feature = "stm32wba52cg")]
+define_peris!(
+    UART = LPUART1, UART_TX = PB5, UART_RX = PA10, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
+    SPI = SPI1, SPI_SCK = PB4, SPI_MOSI = PA15, SPI_MISO = PB3, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
+    @irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
+);
 
 pub fn config() -> Config {
+    // Setting this bit is mandatory to use PG[15:2].
+    #[cfg(feature = "stm32u5a5zj")]
+    embassy_stm32::pac::PWR.svmcr().modify(|w| {
+        w.set_io2sv(true);
+        w.set_io2vmen(true);
+    });
+
     #[allow(unused_mut)]
     let mut config = Config::default();
 
+    #[cfg(feature = "stm32wb55rg")]
+    {
+        config.rcc = embassy_stm32::rcc::WPAN_DEFAULT;
+    }
+
     #[cfg(feature = "stm32f207zg")]
     {
         use embassy_stm32::rcc::*;
@@ -216,16 +262,44 @@ pub fn config() -> Config {
 
     #[cfg(feature = "stm32f429zi")]
     {
-        // TODO: stm32f429zi can do up to 180mhz, but that makes tests fail.
-        // perhaps we have some bug w.r.t overdrive.
-        config.rcc.sys_ck = Some(Hertz(168_000_000));
-        config.rcc.pclk1 = Some(Hertz(42_000_000));
-        config.rcc.pclk2 = Some(Hertz(84_000_000));
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL180,
+            divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
+            divq: None,
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
     }
 
     #[cfg(feature = "stm32f767zi")]
     {
-        config.rcc.sys_ck = Some(Hertz(200_000_000));
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL216,
+            divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz.
+            divq: None,
+            divr: None,
+        });
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+        config.rcc.sys = Sysclk::PLL1_P;
     }
 
     #[cfg(feature = "stm32h563zi")]
@@ -238,7 +312,7 @@ pub fn config() -> Config {
             mode: HseMode::BypassDigital,
         });
         config.rcc.pll1 = Some(Pll {
-            source: PllSource::Hse,
+            source: PllSource::HSE,
             prediv: PllPreDiv::DIV2,
             mul: PllMul::MUL125,
             divp: Some(PllDiv::DIV2),
@@ -249,18 +323,18 @@ pub fn config() -> Config {
         config.rcc.apb1_pre = APBPrescaler::DIV1;
         config.rcc.apb2_pre = APBPrescaler::DIV1;
         config.rcc.apb3_pre = APBPrescaler::DIV1;
-        config.rcc.sys = Sysclk::Pll1P;
+        config.rcc.sys = Sysclk::PLL1_P;
         config.rcc.voltage_scale = VoltageScale::Scale0;
     }
 
-    #[cfg(feature = "stm32h755zi")]
+    #[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = Some(Hsi::Mhz64);
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
         config.rcc.csi = true;
         config.rcc.hsi48 = true; // needed for RNG
-        config.rcc.pll_src = PllSource::Hsi;
         config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV2),
@@ -268,13 +342,14 @@ pub fn config() -> Config {
             divr: None,
         });
         config.rcc.pll2 = Some(Pll {
+            source: PllSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL50,
             divp: Some(PllDiv::DIV8), // 100mhz
             divq: None,
             divr: None,
         });
-        config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
+        config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
         config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
         config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
         config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
@@ -284,11 +359,43 @@ pub fn config() -> Config {
         config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
     }
 
+    #[cfg(any(feature = "stm32h7a3zi"))]
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hsi = Some(HSIPrescaler::DIV1);
+        config.rcc.csi = true;
+        config.rcc.hsi48 = true; // needed for RNG
+        config.rcc.pll1 = Some(Pll {
+            source: PllSource::HSI,
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL35,
+            divp: Some(PllDiv::DIV2), // 280 Mhz
+            divq: Some(PllDiv::DIV8), // SPI1 cksel defaults to pll1_q
+            divr: None,
+        });
+        config.rcc.pll2 = Some(Pll {
+            source: PllSource::HSI,
+            prediv: PllPreDiv::DIV4,
+            mul: PllMul::MUL35,
+            divp: Some(PllDiv::DIV8), // 70 Mhz
+            divq: None,
+            divr: None,
+        });
+        config.rcc.sys = Sysclk::PLL1_P; // 280 Mhz
+        config.rcc.ahb_pre = AHBPrescaler::DIV1; // 280 Mhz
+        config.rcc.apb1_pre = APBPrescaler::DIV2; // 140 Mhz
+        config.rcc.apb2_pre = APBPrescaler::DIV2; // 140 Mhz
+        config.rcc.apb3_pre = APBPrescaler::DIV2; // 140 Mhz
+        config.rcc.apb4_pre = APBPrescaler::DIV2; // 140 Mhz
+        config.rcc.voltage_scale = VoltageScale::Scale0;
+        config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
+    }
+
     #[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))]
     {
         use embassy_stm32::rcc::*;
-        config.rcc.mux = ClockSrc::PLL;
-        config.rcc.hsi16 = true;
+        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.hsi = true;
         config.rcc.pll = Some(Pll {
             source: PLLSource::HSI,
             prediv: PllPreDiv::DIV1,
@@ -299,14 +406,33 @@ pub fn config() -> Config {
         });
     }
 
+    #[cfg(feature = "stm32wl55jc")]
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(32_000_000),
+            mode: HseMode::Bypass,
+            prescaler: HsePrescaler::DIV1,
+        });
+        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.pll = Some(Pll {
+            source: PLLSource::HSE,
+            prediv: PllPreDiv::DIV2,
+            mul: PllMul::MUL6,
+            divp: None,
+            divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG
+            divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2)
+        });
+    }
+
     #[cfg(any(feature = "stm32l552ze"))]
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi16 = true;
-        config.rcc.mux = ClockSrc::PLL;
+        config.rcc.hsi = true;
+        config.rcc.mux = ClockSrc::PLL1_R;
         config.rcc.pll = Some(Pll {
             // 110Mhz clock (16 / 4 * 55 / 2)
-            source: PLLSource::HSI16,
+            source: PLLSource::HSI,
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL55,
             divp: None,
@@ -315,18 +441,28 @@ pub fn config() -> Config {
         });
     }
 
-    #[cfg(feature = "stm32u585ai")]
+    #[cfg(any(feature = "stm32u585ai", feature = "stm32u5a5zj"))]
     {
         use embassy_stm32::rcc::*;
         config.rcc.mux = ClockSrc::MSI(Msirange::RANGE_48MHZ);
     }
 
+    #[cfg(feature = "stm32wba52cg")]
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.mux = ClockSrc::HSI;
+
+        embassy_stm32::pac::RCC.ccipr2().write(|w| {
+            w.set_rngsel(embassy_stm32::pac::rcc::vals::Rngsel::HSI);
+        });
+    }
+
     #[cfg(feature = "stm32l073rz")]
     {
         use embassy_stm32::rcc::*;
         config.rcc.mux = ClockSrc::PLL(
             // 32Mhz clock (16 * 4 / 2)
-            PLLSource::HSI16,
+            PLLSource::HSI,
             PLLMul::MUL4,
             PLLDiv::DIV2,
         );
@@ -337,7 +473,7 @@ pub fn config() -> Config {
         use embassy_stm32::rcc::*;
         config.rcc.mux = ClockSrc::PLL(
             // 32Mhz clock (16 * 4 / 2)
-            PLLSource::HSI16,
+            PLLSource::HSI,
             PLLMul::MUL4,
             PLLDiv::DIV2,
         );