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h7-sai4only-fix
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1826 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
b3879ec223
Merge pull request #2105 from andresv/fix-stm32-uart-set-config 
Fix stm32 uart set_config
 2023-10-24 13:13:42 +00:00
Andres Vahter
bda99e59ec stm32: fix uart parity, add comment why it is so 2023-10-24 15:57:03 +03:00
Andres Vahter
25c2a9baaa stm32 uart: remove redundant set_fifoen(true) 2023-10-24 10:11:54 +03:00
Andres Vahter
1e362c750b stm32 uart: use ConfigError instead of () as error 2023-10-24 09:54:17 +03:00
Andres Vahter
7f72dbdaf2 stm32: fix set_config for buffered uart 
In reconfigure() cr1 register is initialised with write (not modify) which means rxneie and idleneie are disabled after reconfiguration.
 2023-10-24 09:09:33 +03:00
Rasmus Melchior Jacobsen
e8c162ac03 stm32: Remove unneeded unsafe 2023-10-24 07:44:04 +02:00
xoviat
9e230b64a4 stm32/build: deterministically generate data 2023-10-23 18:19:42 -05:00
xoviat
17b4cf8ce7
Merge pull request #2106 from xoviat/fix-stop-2 
stm32: fix low-power test
 2023-10-23 21:29:36 +00:00
xoviat
df4aa0fe25 stm32: fix low-power test 2023-10-23 16:26:34 -05:00
Andres Vahter
188ee59ba6 stm32: fix setting uart databits 2023-10-23 22:40:24 +03:00
Andres Vahter
591612db7e stm32 uart: return error if rx and tx not enabled 2023-10-23 22:39:24 +03:00
Dario Nieuwenhuis
82593bd404 stm32/gpio: make port G work on U5. 2023-10-23 18:12:31 +02:00
Dario Nieuwenhuis
a39ae12edc stm32/rcc: misc cleanups. 2023-10-23 17:36:21 +02:00
Dario Nieuwenhuis
0ef1cb29f7 stm32/rcc: merge wb into l4/l5. 2023-10-23 17:36:21 +02:00
Dario Nieuwenhuis
b9e13cb5d1 stm32/rcc: merge wl into l4/l5. 2023-10-23 00:31:36 +02:00
Dario Nieuwenhuis
412bcad2d1 stm32: rename HSI16 -> HSI 2023-10-22 22:39:55 +02:00
xoviat
7c5f963d1f stm32: fix opamp bug in docs build 2023-10-21 07:32:04 -05:00
Dario Nieuwenhuis
62e1e1637c
Merge pull request #2097 from embassy-rs/rcc-no-spaghetti 
stm32/tests: add stm32h753zi, stm32h7a3zi.
 2023-10-21 02:49:12 +00:00
Dario Nieuwenhuis
3d03c18d4f stm32/tests: add stm32h753zi, stm32h7a3zi. 2023-10-21 04:46:45 +02:00
xoviat
0fb677aad7 stm32: update metapac 2023-10-20 20:21:53 -05:00
Dion Dokter
5b3f75dc72 Merge branch 'master' into center-align 2023-10-20 14:17:55 +02:00
Dion Dokter
6f2995cd4c Invert assert 2023-10-20 10:41:39 +02:00
eZio Pan
241488ef1c bypass ODEN if chip doesn't have it 2023-10-18 19:42:31 +08:00
Dario Nieuwenhuis
f20f170b1f stm32/rcc: refactor and unify f4 into f7. 2023-10-18 05:11:31 +02:00
Dario Nieuwenhuis
67010d123c stm32/rcc: refactor f7. 2023-10-18 05:01:11 +02:00
Dario Nieuwenhuis
361fde35cf stm32/rcc: wait for mux switch. 2023-10-18 04:32:18 +02:00
Dario Nieuwenhuis
7ce3b19389 stm32/rcc: remove unused enum. 2023-10-18 04:32:18 +02:00
xoviat
bbd12c9372 stm32: update metapac 2023-10-17 20:31:44 -05:00
xoviat
683d5c3066
Merge pull request #2077 from xoviat/rcc 
stm32: update metapac
 2023-10-17 01:05:18 +00:00
xoviat
a3574e519a stm32: update metapac 2023-10-16 20:04:10 -05:00
Grant Miller
e7aeb9b29f stm32f1: Keep flash prefetch enabled 2023-10-16 19:23:01 -05:00
Dániel Buga
40e4ca4751 Prepare embassy-net(/-driver,/-driver-channel) 0.2.0 2023-10-16 20:59:06 +02:00
Dario Nieuwenhuis
213b4c9dca time: add links key, release v0.1.5. 2023-10-16 20:11:35 +02:00
Dario Nieuwenhuis
aff77d2b65 stm32/rng: add test. 2023-10-16 05:35:29 +02:00
Dario Nieuwenhuis
18e96898ea stm32/rcc: unify L4 and L5. 2023-10-16 04:00:51 +02:00
Dario Nieuwenhuis
5c5e681819 stm32/rcc: add better support for L4/L4+ differences. 2023-10-16 03:23:43 +02:00
xoviat
b24520579a rcc: ahb/apb -> hclk/pclk 2023-10-15 19:51:35 -05:00
xoviat
1fc35c753b rcc: update pll clock naming 2023-10-15 15:10:42 -05:00
JuliDi
2aaf4bf96b
fix typo in build.rs that caused fmc ClkPin to not be implemented 2023-10-15 19:14:34 +02:00
xoviat
4a156df7a1 stm32: expand rcc mux to g4 and h7 2023-10-14 23:33:57 -05:00
Dario Nieuwenhuis
8a10948ce9 stm32/rcc: port L4 to the "flattened" API like h5/h7. 2023-10-15 03:08:49 +02:00
Dario Nieuwenhuis
3bfbf2697f stm32/rcc: remove unused lse/lsi fields in h7 2023-10-15 01:48:27 +02:00
xoviat
824556c9c8 rcc: remove mux_prefix from clocks 2023-10-14 12:51:45 -05:00
xoviat
575db17264
Merge pull request #2053 from jr-oss/fix_stm32_advanced_timer_enable_output 
STM32: Fix regression in advanced timer to enable output of PWM signa…
 2023-10-14 04:09:57 +00:00
xoviat
3264941c1b rcc mux: update metapac 2023-10-13 23:06:32 -05:00
Ralf
9a7fda87b0 STM32: timer enable_output does not take bool, but just enables the output 2023-10-13 18:52:10 +02:00
Ralf
adc810d24b STM32: Fix regression in advanced timer to enable output of PWM signal by partly reverting commit 74eb519 2023-10-13 17:38:40 +02:00
Scott Mabin
a6bbb130c5 make set_config concrete methods public again 2023-10-12 23:03:33 +01:00
Dániel Buga
02d2c06b23 Release embassy-time 0.1.4 2023-10-12 18:14:33 +02:00
Dario Nieuwenhuis
97ca0e77bf stm32: avoid creating many tiny critical sections in init. 
Saves 292 bytes on stm32f0 bilnky with max optimizations (from 3132 to 2840).
 2023-10-12 16:20:34 +02:00
Dario Nieuwenhuis
66e399b5c6
Merge pull request #2035 from pbert519/stm_reset_and_enable 
STM32: combine RccPeripherals reset() and enable() to enable_and_reset()
 2023-10-12 14:09:13 +00:00
Ulf Lilleengen
01eb1a7339
Merge pull request #2033 from andresovela/stm32-add-timeout-to-i2c 
stm32: add timeout to I2C driver
 2023-10-12 10:44:27 +00:00
pbert
65f81a1f57 Remove critical section for reset 2023-10-12 11:04:45 +02:00
pbert
ecdd7c0e2f enable clock first 2023-10-12 11:04:44 +02:00
pbert
d7d79f3068 Remove workaround for adc v3 2023-10-12 11:04:20 +02:00
pbert
f65a96c541 STM32: combine RccPeripherals reset() and enable() to reset_and_enable() 2023-10-12 11:04:19 +02:00
xoviat
57ccc1051a stm32: add initial rcc mux for h5 2023-10-11 20:59:47 -05:00
Dario Nieuwenhuis
70a91945fc stm32: remove atomic-polyfill. 2023-10-12 02:07:26 +02:00
Andres Oliva
063e6f96da Remove outdated comment 2023-10-11 23:56:21 +02:00
Andres Oliva
e6c47c3718 cargo fmt 2023-10-11 23:47:24 +02:00
Andres Oliva
2f7c2750d1 Feature guarded more unused stuff 2023-10-11 23:45:47 +02:00
Andres Oliva
032b1f2d59 Fix some issues with unused stuff 2023-10-11 23:42:40 +02:00
Andres Oliva
f76d50e837 cfg! macro didn't work, had to duplicate functions with different guards 2023-10-11 23:39:24 +02:00
Andres Oliva
ee5ea7aa06 cargo fmt 2023-10-11 23:34:02 +02:00
Andres Oliva
251d004708 Try using cfg! macro 2023-10-11 23:32:40 +02:00
Andres Oliva
cd68f85501 Added guards to individual APIs 2023-10-11 23:25:13 +02:00
Andres Oliva
b6c0ddb7df Move the feature gates to the i2c module instead of the pub use statement 2023-10-11 23:05:12 +02:00
Andres Oliva
ee93bbf1d4 Gate pub use _version::* 2023-10-11 22:45:54 +02:00
Andres Oliva
1cd3ae9bd5 Add comment about feature gate on I2C mod 2023-10-11 22:20:17 +02:00
Andres Oliva
bfcca79c1e Add time feature back and gate i2c on time 2023-10-11 22:12:03 +02:00
Dario Nieuwenhuis
4a43cd3982 stm32/rcc: LSE xtal is 32768hz, not 32000hz. 
Fixes #2043
 2023-10-11 13:39:04 +02:00
Dario Nieuwenhuis
b91d1eaca0 stm32/rcc: add LSE/LSI to all chips, add RTC to more chips. 2023-10-11 04:12:38 +02:00
Dario Nieuwenhuis
21915a9a3f stm32/rcc: unify L0 and L1. 2023-10-11 01:22:27 +02:00
Dario Nieuwenhuis
d0d0ceec6a stm32/rcc: rename HSE32 to HSE 2023-10-11 01:06:44 +02:00
Dario Nieuwenhuis
0cfa8d1bb5 stm32/rcc: use more PLL etc enums from PAC. 2023-10-11 00:12:33 +02:00
Andres Oliva
cd12c9cbce stm32: add timeout to I2C driver 2023-10-10 18:20:46 +02:00
Andres Vahter
3616d68aaa stm32 flash: check lock bit before unlocking 
It hardfaults if already unlocked flash is unlocked again.
 2023-10-10 12:55:43 +03:00
Gabriel Górski
7526b8edba stm32/eth: Move phy_addr from Ethernet to PHY 
Previously, PHY addressing was a concern of the `Ethernet` struct
which limited the `PHY` implementations which very often have to manage
multiple PHYs internally and thus possibly need to address many of them.

This change extends `StationManagement` to allow addressing different
PHY addresses via SMI.
 2023-10-09 13:46:56 +02:00
Dario Nieuwenhuis
6186fe0807 stm32/rcc: use PLL enums from PAC. 2023-10-09 02:48:22 +02:00
xoviat
2e5ab7981e stm32: update metapac 2023-10-08 18:27:36 -05:00
Dario Nieuwenhuis
9d311121f2
Merge pull request #2022 from HelloWorldTeraByte/impl-pwm-trait 
Implemented Pwm trait from embedded_hal for simple and complementary pwm
 2023-10-07 00:35:05 +00:00
Dario Nieuwenhuis
85c6f23dcb
Merge pull request #2018 from jamesmunns/add-derives 
Add some uncontroversial derives to Error types
 2023-10-07 00:03:10 +00:00
Dario Nieuwenhuis
3bf8e4de5f
Merge pull request #2015 from willglynn/stm32u5_faster_clocks 
stm32: u5: implement >55 MHz clock speeds
 2023-10-06 23:38:15 +00:00
randi
710874021a Implemented Pwm trait for complementary pwm from embedded_hal 2023-10-07 12:22:31 +13:00
Dario Nieuwenhuis
3a8e0d4a27 stm32: implement MCO for all chips. 2023-10-07 01:15:24 +02:00
randi
b217d147de Implemented Pwm trait from embedded_hal 2023-10-07 11:57:19 +13:00
shakencodes
68c4820dde Add MCO support for stm32wl family 2023-10-06 14:37:36 -07:00
Matt Ickstadt
f01609036f h7: implement RTC and LSE clock configuration 2023-10-06 13:28:30 -05:00
James Munns
930b8f3495 Add some uncontroversial derives to Error types 2023-10-06 17:45:35 +02:00
Will Glynn
38e7709a24 stm32: u5: implement >55 MHz clock speeds 
This commit allows STM32U5 devices to operate at 160 MHz.

On STM32U5, MSIS can run at 48 MHz and HSE can reach 50 MHz. Faster
clocks require using PLL1's R output, though PLL1 can serve other
functions besides using the R output for the system clock. This commit
extracts a public `PllConfig` struct, primarily to place associated
constructors on that type, but also with an eye towards enabling the P
and Q outputs in a later commit.

STM32U5 PLLs have various frequency requirements on each stage: after
the `m` prescaler, after the `n` multiplier, and after the `r` divider.
This commit implements the associated checks as assertions.

This commit fixes clock calculation and PLL register configuration
errors in PLL initialization.

STM32U5 has a PWR peripheral which can be configured to push Vcore into
different voltage ranges. System clocks exceeding 55 MHz require range
2, and system clocks exceeding 110 MHz require range 1. This commit
adds `voltage_range` to `Config` and configures PWR as directed.

The voltage range implies different performance limits on various clock
signals, including inside a PLL. This commit implements voltage range
<-> frequency range checks as assertions, and extracts the
otherwise-repeated MSIS, HSI16, and HSE initialization into private
methods on `Config`.

STM32U5 frequencies above 55 MHz require using the PWR EPOD booster.
The EPOD booster requires configuring a second `m` term for PLL1,
`mboost`, such that it falls in a particular range. (Recall that >50
MHz cannot be reached without PLL1, so there is no scenario where EPOD
is needed but PLL1 is not.) This commit configures and enables the EPOD
booster automatically as required.
 2023-10-05 22:13:27 -05:00
xoviat
42176b1a3a
Merge pull request #2013 from xoviat/opamp 
stm32: update metapac and fix opamp ch
 2023-10-04 21:20:42 +00:00
xoviat
e1a0635ca3 stm32: update metapac and fix opamp ch 2023-10-04 16:15:08 -05:00
Gabriel Górski
c6513f93fe stm32/gpio: Implement eh1::digital::InputPin for OutputOpenDrain 
Pins in open-drain mode are outputs and inputs simultaneously.
 2023-10-04 18:20:25 +02:00
Dario Nieuwenhuis
0324cee0ca update embedded-io, embedded-nal-async. 2023-10-04 00:10:55 +02:00
xoviat
0c4cddfafb Merge branch 'main' of github.com:embassy-rs/embassy into opamp 2023-10-03 16:44:44 -05:00
xoviat
e561e673c2 stm32: add opamp mod and update pac 2023-10-03 16:34:13 -05:00
xoviat
bb8a1b7f1f wpan: re-enable HIL tests 2023-10-03 15:53:22 -05:00
Dario Nieuwenhuis
6e901846df
Merge pull request #1995 from JuliDi/quadspi 
[STM32] QUADSPI support bank 2
 2023-10-03 01:55:27 +00:00
xoviat
bc203ebe4b Merge branch 'main' of github.com:embassy-rs/embassy into fix-stop 2023-10-02 18:30:41 -05:00
xoviat
e042b3056d stm32: fix stop 2023-10-02 18:11:03 -05:00