Commit Graph

987 Commits

Author SHA1 Message Date
bors[bot]
6264fe39a5
Merge #839
839: Misc LoRaWAN improvements r=lulf a=timokroeger

Trying too get `embassy-lora` running on a [LoRa-E5 Dev Board](https://wiki.seeedstudio.com/LoRa_E5_Dev_Board/).
I can see the join message arriving in the The Things Network console but the device does not receive the accept message yet.
Opening this PR anyway because I think there are some nice things to decouple the lora crate from the nucleo board.

`@lulf` Could you test if this PR breaks your LoRa setup? Marking as draft for the time being.

Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-09-04 07:17:23 +00:00
Dario Nieuwenhuis
5327b9c289 time: add more tick rates, use 1mhz as default. 2022-09-02 00:59:34 +02:00
Dario Nieuwenhuis
8ba421f324 Do not use cfg_if for embedded-hal-async feature gates.
Old code used `cfg_if!` because rustc still parses code inside disabled cfg's, and Rust stable at that time couldn't parse the new GAT where-clause location. This is not the case anymore.
2022-08-31 03:11:21 +02:00
Timo Kröger
308ca4b8e3 Use pub(crate) visibility for internal SPI
SubGhz provides a public interface for the radio connected to internal SPI
`#[allow(dead_code)]` is required for CI to succeed
2022-08-26 15:44:58 +02:00
Timo Kröger
84240d49ea stm32wl: Fix RCC
* `MSIRGSEL = 1` was required for MSI accept the updated MSI range
* Reorder enable and clock switching to properly handle the jump from
the default 4MHz MSI to a higher MSI freuquency
2022-08-26 15:44:58 +02:00
Timo Kröger
61c666212f stm32wl: Do not require external SPI pins for SUBGHZ
For the Seeed Studio Lora-E5 those pins conflict with the radio frontend control GPIOS (PA4 and PA5).
2022-08-26 15:42:25 +02:00
Dario Nieuwenhuis
21072bee48 split embassy-util into embassy-futures, embassy-sync. 2022-08-22 22:18:13 +02:00
Vincent Stakenburg
51359e7d24 fix lpuart implementation when there isn't one present 2022-08-19 15:27:11 +02:00
Vincent Stakenburg
a833e02363 implement support for LPUART 2022-08-19 12:05:19 +02:00
Dario Nieuwenhuis
5daa173ce4 Split embassy-time from embassy-executor. 2022-08-18 01:22:30 +02:00
Dario Nieuwenhuis
fc6e1e06b3 Remove HAL initialization from #[embassy::main] macro. 2022-08-17 22:16:46 +02:00
Dario Nieuwenhuis
67edea4168 Update to critical-section 1.0, atomic-polyfill 1.0 2022-08-17 19:01:56 +02:00
Dario Nieuwenhuis
2649f13dc7 stm32/rcc: fix unnecessary parentheses 2022-08-17 15:03:23 +02:00
Dario Nieuwenhuis
72cd015c1a stm32/sdmmc: remove cast no longer allowed on latest nightly due to nonexhaustive enum. 2022-08-17 14:44:18 +02:00
chemicstry
936473b68a Make sda/scl pullups separate as in nRF HAL 2022-08-10 12:36:15 +03:00
chemicstry
6498324b58 Implement I2C pullup configuration 2022-08-09 22:13:35 +03:00
chemicstry
206b7fd8ed Use RccPeripheral for DAC and add a hackfix for H7 2022-08-04 03:31:47 +03:00
chemicstry
5f01e56728 Merge v1, v2 DAC and update register definitions 2022-08-04 03:02:57 +03:00
Dario Nieuwenhuis
a0f1b0ee01 Split embassy crate into embassy-executor, embassy-util. 2022-07-29 23:40:36 +02:00
chemicstry
42434c75bc Make vref units explicit 2022-07-27 14:13:59 +03:00
chemicstry
b1f0d6320e Improve set_vref docs 2022-07-27 01:30:32 +03:00
chemicstry
046778fc53 Improve ADC configuration options 2022-07-27 01:17:26 +03:00
bors[bot]
84cffc751a
Merge #876
876: Add defmt support to embassy-embedded-hal errors r=Dirbaio a=matoushybl

`defmt::unwrap!()` should now work with shared buses. I tested it only with I2C as I don't have SPI in the target project.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-07-24 20:15:57 +00:00
Matous Hybl
c38755c5b7 Add defmt support to embassy-embedded-hal errors 2022-07-24 22:10:50 +02:00
Dario Nieuwenhuis
b5ff7c5d60 rename PwmPin::new_chX, update examples. 2022-07-23 16:16:29 +02:00
Ben Gamari
042e11960e embassy-stm32/pwm: Generalize channel selection
550da471be previously refactored the STM32
PWM logic in such a way to preclude use of non-contiguous channels (e.g.
channel 2 but not channel 1). Refactor it yet again to yet again allow
this sort of usage.
2022-07-23 15:57:13 +02:00
Dario Nieuwenhuis
19d1ef0e29 stm32/gpio: Add Peripheral<Self> bound to Pin. 2022-07-23 14:28:42 +02:00
Dario Nieuwenhuis
4901c34d9c Rename Unborrowed -> PeripheralRef, Unborrow -> Peripheral 2022-07-23 14:00:19 +02:00
Dario Nieuwenhuis
8a9d2f59af Update embassy-stm32 2022-07-23 02:40:13 +02:00
Dario Nieuwenhuis
be6408e202 Rename unsafe_impl_unborrow to impl_unborrow 2022-07-23 01:33:22 +02:00
bors[bot]
9d388d357a
Merge #866
866: F4 flash fixes r=Dirbaio a=chemicstry

This discontinuous flash sector layout is too cursed and I left some mistakes in last PR. Erasing last sector did not work and it wasn't possible to erase between memory banks for 1MB dual-bank devices. So I changed the erase function to iterate over memory addresses (which is continuous) instead of sector numbers.

It should also be possible to implement erase across memory banks for H7, but it requires special handling for write too. I don't have an H7 to test now so left it as is.

I wasn't sure how to add tests to `embassy-stm32` and it seems that there are none, except for `subghz`, but no test runner? Anyway, I tested the `get_sector` on playground: https://play.rust-lang.org/?version=stable&mode=debug&edition=2021&gist=13b59339fe6c70a3249e6183e81f869e

Also fixed erase alignment requirements on `Flash::blocking_erase()`, as it previously only checked alignment on size, but not on offsets.

P.S. the diff is a bit messed up, I recommend looking at files directly

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-07-15 06:19:05 +00:00
chemicstry
f0027c9fe0 Require erase address to be aligned to page size 2022-07-14 21:21:46 +03:00
chemicstry
5a265661bb Fix erasing across banks 2022-07-14 20:58:01 +03:00
chemicstry
039acda3a8 Fix writing to last sector of F4 flash 2022-07-14 19:41:39 +03:00
chemicstry
53e40860c1 Move all gpio logic to Flex 2022-07-13 02:45:37 +03:00
chemicstry
a335589f34 Change get_set_level to get_output_level 2022-07-13 02:25:09 +03:00
chemicstry
329955f718 Use Into conversions instead of matches 2022-07-13 02:08:31 +03:00
chemicstry
98dcce81ca Add more convenience GPIO functions 2022-07-13 01:43:22 +03:00
chemicstry
2df665da8a Revert "Make advanced timer trait not require general purpose timer trait as the timers are too different."
This reverts commit 4988dfe981.
2022-07-12 15:11:57 +03:00
bors[bot]
2adee4af38
Merge #858
858: embassy-stm32: Simplify time r=Dirbaio a=GrantM11235

- Remove unused `MilliSeconds`, `MicroSeconds`, and `NanoSeconds` types
- Remove `Bps`, `KiloHertz`, and `MegaHertz` types that were only used
for converting to `Hertz`
- Replace all instances of `impl Into<Hertz>` with `Hertz`
- Add `hz`, `khz`, and `mhz` methods to `Hertz`, as well as
free function shortcuts
- Remove `U32Ext` extension trait

Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-07-11 02:51:06 +00:00
Grant Miller
5ecbe5c918 embassy-stm32: Simplify time
- Remove unused `MilliSeconds`, `MicroSeconds`, and `NanoSeconds` types
- Remove `Bps`, `KiloHertz`, and `MegaHertz` types that were only used
for converting to `Hertz`
- Replace all instances of `impl Into<Hertz>` with `Hertz`
- Add `hz`, `khz`, and `mhz` methods to `Hertz`, as well as
free function shortcuts
- Remove `U32Ext` extension trait
2022-07-10 21:46:45 -05:00
bors[bot]
99f4fd33b4
Merge #859
859: Add F4 flash driver r=Dirbaio a=chemicstry

Pending on https://github.com/embassy-rs/stm32-data/pull/152

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-07-11 01:37:19 +00:00
chemicstry
3271ba36e4 Fix cfg flags 2022-07-11 04:07:28 +03:00
chemicstry
734c38eb9c Add F4 flash driver 2022-07-11 03:57:46 +03:00
bors[bot]
9753f76794
Merge #810
810: Takes care of power for nRF USB devices r=Dirbaio a=huntc

Modifies the usb-serial example to illustrate how to setup USB for situations where the USB power can be detected and removed.

Gaps:

~~* No support for the nrf-softdevices as yet, although this should be possible via another constructor.~~
* No support for the nrf5340, although this should be possible via USBREG.

The change is tested and appears to work. Some notes:

* There's an existing field named self_powered as a UsbDevice field. It doesn't ever appear to get set. I'm wondering if this field is intended to signal that a device has the nRF VBUS power situation or not. I'm not presently using it.
* The new PowerDetected event is generated on the bus initially in situations where just new is used i.e. without power management, including on STM. We can therefore rely on this event always being generated.

Old description:

~~EnabledUsbDevice is a wrapper around the `UsbDevice` where its enablement is also subject to external events, such as `POWER` events for nRF. It is introduced generically to support other platforms should they also require external signaling for enablement.~~

Co-authored-by: huntc <huntchr@gmail.com>
2022-07-11 00:01:41 +00:00
bors[bot]
c6a11db39e
Merge #854
854: Implement IWDG timeout calculation r=Dirbaio a=chemicstry

Allow specifying `IndependentWatchdog` timeout as `Duration` instead of prescaler value.

Since IWDG is clocked from LSI, which differs between families, I standardized HSI/LSI definitions in RCC and used that.

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-07-10 21:45:34 +00:00
chemicstry
5a208d28d0 Fix g0 rcc build 2022-07-11 00:37:00 +03:00
bors[bot]
93e7d53e39
Merge #851
851: Gpio dynamic flex r=Dirbaio a=AntoineMugnier

Add Flex GPIO type for embassy-stm32 as it is the case for  embassy-nrf.


Co-authored-by: amugniere@gmail.com <antoine.mugnier@depixus.com>
2022-07-10 21:22:46 +00:00
chemicstry
d7d1e46a5f Use u32 instead of Duration for IWDG 2022-07-11 00:00:33 +03:00
amugniere@gmail.com
323b0d1a5c Have removed ANOTHER redondant ErrorType trait impl 2022-07-10 22:01:48 +02:00
amugniere@gmail.com
1eca026ebd Have removed redondant ErrorType trait impl 2022-07-10 21:36:04 +02:00
amugniere@gmail.com
e4a36e1d98 rustfmt on previously edited files 2022-07-10 21:08:12 +02:00
amugniere@gmail.com
53388d4576 have adapted access to pin() and port() methods of Sealed::Pin in exti.rs according to previous changes on Input struct 2022-07-10 20:55:04 +02:00
chemicstry
3bf1e1d4aa Fix f2, wl compilation 2022-07-10 21:46:14 +03:00
chemicstry
f43545f36e Fix warnings 2022-07-10 21:16:54 +03:00
chemicstry
85054a7233 Fix typo 2022-07-10 21:15:38 +03:00
chemicstry
1fd5022e72 Refactor IWDG to use LSI frequency from RCC 2022-07-10 20:59:36 +03:00
chemicstry
bd01e90bfa Implement IWDG timeout calculation 2022-07-10 20:38:30 +03:00
bors[bot]
5f43c1d37e
Merge #850
850: Shared buses with SetConfig r=Dirbaio a=kalkyl

Addresses issue #830 

Co-authored-by: Henrik Alsér <henrik@mindbite.se>
2022-07-10 00:03:44 +00:00
Henrik Alsér
baae64d911 Add embassy-embedded-hal nightly feature 2022-07-09 23:41:02 +02:00
amugniere@gmail.com
fa3e1ab68a correction of the access to flex pin attribute in gpio_v2 2022-07-09 14:06:47 +02:00
Henrik Alsér
880b71a1e8 impl SetConfig for stm32 i2c and SPI 2022-07-09 02:28:05 +02:00
amugniere@gmail.com
39702d7624 set_as_input_output() and set_as_output() : Have added comments and made functions public 2022-07-08 21:46:16 +02:00
Henrik Alsér
43aec9083c Cleanup 2022-07-08 08:03:38 +02:00
Dario Nieuwenhuis
01ef03f446 stm32/i2c: impl ErrorType for all. 2022-07-07 15:46:30 +02:00
Henrik Alsér
399e7a4791 NoDma 2022-07-07 15:46:30 +02:00
Henrik Alsér
be731b222e Cleanup 2022-07-07 15:46:30 +02:00
Henrik Alsér
0fe818f4f8 v1 fix 2022-07-07 15:46:30 +02:00
Henrik Alsér
1ed5b387f9 v2 fix 2022-07-07 15:46:30 +02:00
Henrik Alsér
02812754ec rustfmt 2022-07-07 15:46:30 +02:00
Henrik Alsér
2460d21fa4 Add EH 1.0 impls for stm32 i2c 2022-07-07 15:46:30 +02:00
huntc
4a8f117f25 Puts in the machinery to handle power detected/removed 2022-07-07 10:08:57 +10:00
amugniere@gmail.com
4e54d09ab1 Have added OutputOpenDrain with Flex 2022-07-04 22:38:05 +02:00
amugniere@gmail.com
13b259d7cd Have added Flex to eh01 and eh2 2022-07-04 22:19:02 +02:00
amugniere@gmail.com
359fc4d124 Flex GPIO implementation : Output 2022-06-30 23:03:15 +02:00
amugniere@gmail.com
f05082b9a3 have reverted changed in mod eh1 from previous commit 2022-06-30 22:55:57 +02:00
amugniere@gmail.com
9b3c5af92a Flex GPIO implementation : Input 2022-06-30 22:50:53 +02:00
Vincent Stakenburg
d1d07cd9e3 fix case when chip has multiple iwdg 2022-06-28 13:22:43 +02:00
Vincent Stakenburg
f2ad9c2d9d rebase and fix unborrow 2022-06-28 12:51:08 +02:00
Vincent Stakenburg
74bbf5aa02 address review 2022-06-28 12:46:17 +02:00
Vincent Stakenburg
5cf3fbece4 initial independent watchdog implementation 2022-06-28 12:46:17 +02:00
Dario Nieuwenhuis
42bc510eff Remove STM32L485 "ghost chips" 2022-06-27 02:47:15 +02:00
Dario Nieuwenhuis
a855889f70 Update stm32-data 2022-06-27 02:10:01 +02:00
Dario Nieuwenhuis
948bb93dc2 docs: Add $COMMIT to git srclinks. 2022-06-26 23:55:38 +02:00
Dario Nieuwenhuis
397722c328 stm32: fix f100 build. 2022-06-26 23:52:38 +02:00
bors[bot]
84628d36cf
Merge #826
826: Bump bxcan version r=chemicstry a=chemicstry



Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-06-22 23:48:45 +00:00
chemicstry
3cdd8c1aeb Fix PWM for advanced timers 2022-06-23 02:27:39 +03:00
chemicstry
31177d994f Fix example 2022-06-23 02:01:23 +03:00
chemicstry
2d2f9e39b9 Bump bxcan version 2022-06-23 01:42:21 +03:00
Dario Nieuwenhuis
1f746e0939 Remove the authors field from Cargo.tomls
It currently contains whoever was first to write some code for the crate,
even if many more people have contributed to it later.

The field is "sort of" deprecated, it was made optional recently:
https://rust-lang.github.io/rfcs/3052-optional-authors-field.html

Due the the reasons listed there I believe removing it is better than
setting it to generic fluff like "The Embassy contributors".
2022-06-18 02:16:40 +02:00
Dario Nieuwenhuis
88e36a70bd
Update to 2021 edition. (#820) 2022-06-18 02:15:48 +02:00
Daniel Bevenius
9031b8f80a Fix doc comments for BpskPacketParams 2022-06-16 07:34:59 +02:00
Daniel Bevenius
d0edd171f8 Fix typo in LoRaPacketParams::new doc 2022-06-16 06:22:03 +02:00
Ulf Lilleengen
faa59efbf6 Cargo fmt 2022-06-15 09:01:22 +02:00
Ulf Lilleengen
3696226fe8 Sync subghz peripheral support with stm32wlxx-hal 2022-06-14 16:27:42 +02:00
Dario Nieuwenhuis
a8703b7598 Run rustfmt. 2022-06-12 22:22:31 +02:00
Dario Nieuwenhuis
5085100df2 Add embassy-cortex-m crate.
- Move Interrupt and InterruptExecutor from `embassy` to `embassy-cortex-m`.
- Move Unborrow from `embassy` to `embassy-hal-common` (nothing in `embassy` requires it anymore)
- Move PeripheralMutex from `embassy-hal-common` to `embassy-cortex-m`.
2022-06-12 21:45:38 +02:00
Dario Nieuwenhuis
db344c2bda
common/PeripheralMutex: remove unsafe API. (#802)
Following the project's decision that "leak unsafe" APIs are not marked as "unsafe",
update PeripheralMutex to accept non-'static state without unsafe.

Fixes #801
2022-06-09 21:28:13 +02:00
Ulf Lilleengen
7d64f5cda7 Use correct index and bank 2022-06-07 15:59:22 +02:00
Dario Nieuwenhuis
3e4bead321 stm32: add USB driver. 2022-06-07 03:29:00 +02:00
Dario Nieuwenhuis
0aa73f58e2 Update stm32-metapac. 2022-06-07 00:28:26 +02:00
chemicstry
b0ffd9a1cc Fix AF pullup configuration for GPIOv1 2022-06-06 17:12:52 +03:00
Will Glynn
34a8a64bf5 stm32: make tick rate configurable
The stm32 time drivers support arbitrary tick rates but the associated
Cargo features do not. Enabling any time driver presently enables
`embassy/time-tick-32768hz`; instead, enable only `embassy/time`.

This is a breaking change: users must now choose a tick rate. The
previous behavior is available by enabling the
`embassy/time-tick-32768hz` feature, but now users may also choose
`embassy/time-tick-1000hz` or `embassy/time-tick-1mhz` instead.
2022-05-30 20:13:25 -05:00
bors[bot]
70e4418df9
Merge #781 #785
781:  embassy-net v2 r=Dirbaio a=Dirbaio

- No more `dyn`
- It's no longer a global singleton, you can create muliple net stacks at once.
  - You can't tear them down though, the Device it still has to be `'static` due to restrictions with smoltcp's "fake GAT" in the Device trait. :(
- Removed `_embassy_rand` hack, random seed is passed on creation.



785: stm32: g0: add PLL clock source r=Dirbaio a=willglynn

STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at 16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach 64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q` to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main reason the user will configure the PLL, so `r` is mandatory and the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the MCO and MCO2 peripherals, so `q` is optional and the output is conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()` calls `PllConfig::init()` which initializes the PLL per [RM0454]. It disables the PLL, waits for it to stop, enables the source oscillator, configures the PLL, waits for it to lock, and then enables the appropriate outputs. `rcc::init()` then switches the clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This was likely a blocker for anyone using HSE >= 24 MHz, with or without the PLL.) Flash accesses are now automatically slowed down as needed before changing the clock source, and sped up as permitted after changing the clock source. The number of flash wait states also determines if flash prefetching will be profitable, so that is now handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Co-authored-by: Will Glynn <will@willglynn.com>
2022-05-31 00:25:21 +00:00
Dario Nieuwenhuis
6320e30adf Update embedded-hal-async to 0.1.0-alpha.1 2022-05-29 22:34:08 +02:00
Will Glynn
1c2b27dcad embassy-stm32: g0: add PLL clock source
STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at
16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach
64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks
its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q`
to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main
    reason the user will configure the PLL, so `r` is mandatory and
	the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S
    peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the
    MCO and MCO2 peripherals, so `q` is optional and the output is
	conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()`
calls `PllConfig::init()` which initializes the PLL per [RM0454]. It
disables the PLL, waits for it to stop, enables the source
oscillator, configures the PLL, waits for it to lock, and then
enables the appropriate outputs. `rcc::init()` then switches the
clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash
wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz
requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This
was likely a blocker for anyone using HSE >= 24 MHz, with or without
the PLL.) Flash accesses are now automatically slowed down as needed
before changing the clock source, and sped up as permitted after
changing the clock source. The number of flash wait states also
determines if flash prefetching will be profitable, so that is now
handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
2022-05-27 23:56:42 -05:00
chemicstry
1d951a54be Reimplement BufRead for BufferedUart 2022-05-26 14:02:55 +03:00
Dario Nieuwenhuis
a5aea995a8 WIP embassy-net v2 2022-05-25 19:56:22 +02:00
Dario Nieuwenhuis
d0fe9af458
Merge pull request #771 from embassy-rs/net-split
net: add split() to tcpsocket
2022-05-19 07:13:24 +02:00
Dario Nieuwenhuis
e3b8e35498 Make embassy-net nightly-only.
It's useless without async traits, so juggling the `nightly` feature
around is not worth the pain.
2022-05-19 06:15:01 +02:00
bors[bot]
7743b8e1ae
Merge #776
776: Automatically set ADC clock prescaler on v2 ADC to respect max frequency r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-05-19 04:00:23 +00:00
Dario Nieuwenhuis
47ceee47d5 Update embedded-io to 0.3 2022-05-19 00:36:18 +02:00
Matous Hybl
53f65d8b09 Automatically set ADC clock prescaler on v2 ADC to respect max frequency 2022-05-18 18:34:36 +02:00
Ralf
c90968bb70 stm32/rcc: Modify only relevant CFGR bits and keep the settings previously done.
PLL settings remained intact because these bits are not writable when PLL is enabled,
but prescaler settings were overwritten by selecting PLL as sysclk (CFGR.SW[1:0]).
2022-05-12 09:09:39 +02:00
Ralf
1a216958ac stm32/rcc: Set flash prefetch buffer and half cycle access according to AHB clock prescaler 2022-05-12 09:09:39 +02:00
Ralf
f4677469f9 stm32/usart: Data length is including parity. To get e.g. 8E1 you need to choose 9 data bits 2022-05-12 09:09:30 +02:00
Matous Hybl
01fb447e9d Allow maximal clock for F7 HCLK 2022-05-08 23:07:28 +02:00
bors[bot]
e9ab960ebf
Merge #760
760: stm32/gpio: Add support for `set_speed` for gpio v1 r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-05-08 19:53:31 +00:00
Grant Miller
acc1761637 Remove unnecessary cfg 2022-05-08 14:50:15 -05:00
Grant Miller
b230ac9c1a stm32/gpio: Add support for set_speed for gpio v1 2022-05-08 14:43:37 -05:00
Dario Nieuwenhuis
96d0eb9476 stm32: Fix stm32f107 build. 2022-05-08 21:37:37 +02:00
bors[bot]
a4bf190f2f
Merge #752
752: Replace embassy::io with embedded_io. r=Dirbaio a=Dirbaio

TODO:

- [x] Release embedded-io on crates.io
- [x] Remove git dep

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-05-06 23:54:07 +00:00
Dario Nieuwenhuis
931a137f8c Replace embassy::io with embedded_io. 2022-05-07 01:45:54 +02:00
Matous Hybl
118532278c Add H7 flash and bootloader support 2022-05-06 21:57:15 +02:00
Matous Hybl
6d56f772e1 Add F7 flash and bootloader support 2022-05-06 21:57:15 +02:00
Matous Hybl
f3700b4e42 Refactor flash handling to different modules for different families 2022-05-06 21:57:15 +02:00
Matous Hybl
4f5088d79d Add support for F3 flash 2022-05-06 21:57:15 +02:00
Dario Nieuwenhuis
fc32b3750c Remove embassy_hal_common::usb.
The replacement is `embassy-usb`. There's a WIP driver for stm32 USBD in #709,
there's no WIP driver for stm32 USB_OTG. This means we're left without
USB_OTG support for now.

Reason for removing is I'm going to soon remove `embassy::io`, and
USB uses it. I don't want to spend time maintaining "dead" code
that is going to be removed. Volunteers welcome, either to update
old USB to the new IO, or write a USB_OTG driver fo the new USB.
2022-05-04 01:41:37 +02:00
Dario Nieuwenhuis
49ae26f384
Merge pull request #748 from embassy-rs/nrf-i2c-timeout
Misc HAL improvements.
2022-05-03 01:25:05 +02:00
Dario Nieuwenhuis
71e46d7efd stm32/gpio: add EH1.0 trait impls. 2022-05-03 00:52:48 +02:00
bors[bot]
6e129cf34f
Merge #747
747: stm32/adc/v4: Fix log statement r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-05-02 20:18:01 +00:00
Grant Miller
4bccd77849 stm32/adc/v4: Fix log statement 2022-05-02 15:14:49 -05:00
Dario Nieuwenhuis
a5f5c3a844 net: add functions to get current Eth and IP config 2022-05-02 16:19:34 +02:00
bors[bot]
d600f39260
Merge #743
743: Add PLL config support for F2 r=Dirbaio a=Gekkio

- minor changes to make the F2 RCC API a bit more flexible
- low-level PLL config with assertions based on datasheet specs. It shouldn't be very difficult to later add a "reverse API" where you pass the clocks you want to a function and it generates a `PLLConfig` struct for you
- PLL API tested on my custom board with 12 MHz HSE as source for PLL to generate max clocks for SYSCLK/AHB/APB/APB1/PLL48
- the example *should* work but is untested since I don't have the Nucleo board 😞 

Co-authored-by: Joonas Javanainen <joonas.javanainen@gmail.com>
2022-04-30 21:08:43 +00:00
Joonas Javanainen
e88559c5ca
Use defmt-friendly error handling 2022-04-30 11:41:17 +03:00
Dario Nieuwenhuis
804b20c5af stm32/eth: make "ethmac" vs "eth" consistent in RCC regs. 2022-04-30 04:49:57 +02:00
David Lenfesty
5e6c4ae024 embassy-stm32/eth: consolidate v1a/v1c and add v1b
The only differences between v1a and v1c were clocks and GPIO, v1b will
likely work out of the box (or simply need minor tweaks)
2022-04-30 04:49:24 +02:00
David Lenfesty
2e7b42fc5b embassy-stm32/eth: convert LAN8742 driver to generic SMI driver
SMI Ethernet PHYs all share a common base set of registers that can do
90% of all tasks. The LAN8742 driver used some vendor-specific
registers to check link negotiation status, but the need for that was
debatable, so I migrated it to a generic driver instead, anybody who
wants extra functionality can copy it and impl their own on top of it.
2022-04-30 04:49:24 +02:00
David Lenfesty
905b40e212 embassy-stm32/eth/v1a: configure pins correctly for f107
v1a works correctly!
2022-04-30 04:49:24 +02:00
David Lenfesty
0d2ef1099b initial work porting eth to f107 2022-04-30 04:49:24 +02:00
David Lenfesty
f30e5d2d3f Initial import to v1a, does not compile 2022-04-30 04:49:24 +02:00
Joonas Javanainen
07ad52162b
Add PLL config support for F2 2022-04-29 18:21:40 +03:00
Joonas Javanainen
0cfe1dc9df
Move HSE config out of main clock mux
This makes the configuration more flexible and closer to the underlying
configuration register structure. For example, we could use HSI for the
system clock, but use HSE to output a clock with MCO.
2022-04-29 17:51:18 +03:00
Matous Hybl
7538f57d62 Remove unnecessary feature gating for giant transfers in DCMI 2022-04-27 16:53:20 +02:00
Ulf Lilleengen
da61611f8f Add bootloader to CI 2022-04-27 15:17:18 +02:00
Ulf Lilleengen
484e0acc63 Add stm32 flash + bootloader support
* Add flash drivers for L0, L1, L4, WB and WL. Not tested for WB, but
should be similar to WL.
* Add embassy-boot-stm32 for bootloading on STM32.
* Add flash examples and bootloader examples
* Update stm32-data
2022-04-27 15:17:18 +02:00
Dario Nieuwenhuis
009bb8e4e1 stm32: add stm32u5 GPDMA, SPIv4 support, add HIL tests. 2022-04-27 01:16:14 +02:00
Matous Hybl
945fa0871f Implement giant (chunked) DMA transfers for DCMI. 2022-04-25 14:30:43 +02:00
Dario Nieuwenhuis
3251a21fb7 Switch to crates.io embedded-hal, embedded-hal-async.
This temporarily removes support for the async UART trait, since it's
not yet in embedded-hal-async.
2022-04-22 19:58:24 +02:00
Dario Nieuwenhuis
e5a843dc06 net: auto-enable defmt in smoltcp using namespaced features. 2022-04-13 17:46:27 +02:00
bors[bot]
6d0e6d563d
Merge #714
714: add more clock options for l4 and l5 r=Dirbaio a=ant32

- added an assert so it panics if pll48div is not 48Mhz
- added MSI as a clock source for PLL
- removed hsi48 option for MCUs mentioned in l4 rcc presentation
- copied some code from l4 to l5, but don't have a way of testing it.

Co-authored-by: Philip A Reimer <antreimer@gmail.com>
2022-04-12 21:42:36 +00:00
bors[bot]
77c2b151c2
Merge #715
715: stm32/dac: Check proper channel r=Dirbaio a=michalsrb

Small fix. Otherwise it panics when trying to use channel 1 if channel 2 does not exist.

Co-authored-by: Michal Srb <michalsrb@gmail.com>
2022-04-12 20:57:36 +00:00
Matous Hybl
371f3ef419 Add ADC support for H7 2022-04-12 22:25:00 +02:00
Michal Srb
c1914a477d stm32/dac: Check proper channel 2022-04-12 12:49:06 +02:00
Philip A Reimer
d90ecbbe40 add more clock options for l4 and l5 2022-04-11 19:11:02 -06:00
Philip A Reimer
d8860c0b80 add stm32l4 hsi48 and usb example 2022-04-09 14:55:03 -06:00
Dario Nieuwenhuis
8b757e1aec Add stm32wlexx support 2022-04-08 03:43:58 +02:00
Dario Nieuwenhuis
0c07d03754 Add missing stm32wl/stm32wb chips except stm32wle 2022-04-08 03:15:27 +02:00
Dario Nieuwenhuis
50ff63ab88 Add STM32L5 support. 2022-04-08 03:11:38 +02:00
Matous Hybl
eb6910fa86 Reexport unborrow macro in HALs 2022-04-07 12:57:02 +02:00
Dario Nieuwenhuis
aee19185b7 Add more docserver metadata. 2022-04-05 21:05:09 +02:00
Philip A Reimer
1f59f8e7d0 add pllsai1 and allow for 120Mhz clock on stm32l4+ 2022-04-01 22:42:43 -06:00
chemicstry
d052631118 Fix STM32 timer interrupt bug 2022-03-30 00:27:33 +03:00
Joonas Javanainen
83211c2b61
Add workaround for F2 errata 2022-03-27 19:00:36 +03:00
Joonas Javanainen
a608d0deaf
Add minimal STM32F2 RCC
No support for PLL or other clocks than SYSCLK/AHB/APB1/APB2
2022-03-27 18:40:49 +03:00
Joonas Javanainen
08e6a996bc
Regenerate embassy-stm32 features 2022-03-21 00:19:36 +02:00
bors[bot]
37ada65a33
Merge #669
669: Add SDMMC v1 and SDIO support r=Dirbaio a=chemicstry

SDMMC v2 peripheral is an extension of SDMMC v1 (or SDIO) so I managed to reuse most of the code, with some cfg's.

Apart from small differeces in registers, the biggest change is that v2 uses internal DMA, while v1 has to use shared DMA peripheral. This makes code a bit uglier, because DMA channel for v1 has to be passed around. Not sure if it's possible to make it any cleaner.

This also adds `TransferOptions` structure to DMA, because SDMMC v1 requires setting peripheral flow control and burst transfers. Let me know if some alternative way would be prefered.

I tested this on STM32F429ZIT6 (with sd card) and STM32H745ZIT6 (with oscilloscope).

Depends on: https://github.com/embassy-rs/stm32-data/pull/130

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-03-20 20:19:58 +00:00
bors[bot]
f0a071790d
Merge #673
673: Inline GPIO functions r=Dirbaio a=nviennot

All GPIO functions are monomorphized (per pin). Inlining these make the ROM smaller when using opt-level="z"

Co-authored-by: Nicolas Viennot <nicolas@viennot.biz>
2022-03-19 20:34:07 +00:00
Nicolas Viennot
4aba87f983 Inline GPIO functions
All GPIO functions are monomorphized (per pin). Inlining these make the
ROM smaller when using opt-level="z"
2022-03-19 14:06:11 -04:00
chemicstry
bdeb537ffa Fix compile for stm32wb 2022-03-18 01:33:39 +02:00
chemicstry
b30a42aff8 Fix RCC safety and add reset to DAC 2022-03-18 01:16:07 +02:00
chemicstry
ca88ace98d Reset peripherals on enable 2022-03-18 00:46:46 +02:00
chemicstry
d26b751edc Add comments 2022-03-17 19:41:44 +02:00
chemicstry
051c6350ea Make UART futures Send 2022-03-17 18:23:47 +02:00
chemicstry
c24d482d51 Fix DMA channels 2022-03-17 01:54:56 +02:00
chemicstry
24a9e19062 More cleanup 2022-03-17 01:12:29 +02:00
chemicstry
9d71acc49e Cleanup 2022-03-16 23:55:07 +02:00
chemicstry
224071f08e Add F7 example 2022-03-16 23:44:02 +02:00
chemicstry
ea467e0acb Rename DMA trait 2022-03-16 20:30:57 +02:00
chemicstry
8a8e5c4b73 Fix SDMMC v2 and add H7 example 2022-03-16 20:20:39 +02:00
chemicstry
48fc48ea7d Fix BDMA 2022-03-16 19:41:34 +02:00
chemicstry
bf4a38ac06 Use RCC frequency instead of config 2022-03-16 19:09:37 +02:00
chemicstry
6d547b1143 SDIO working on stm32f4 2022-03-16 18:52:27 +02:00
chemicstry
34b5175d2c Add more options to DMA 2022-03-16 18:52:06 +02:00
chemicstry
2d224cf6a0 Update 2022-03-15 19:58:19 +02:00
Ulf Lilleengen
e09bde9345 Add support for splitting stm32 usart into TX and RX
* Keeps existing API for usart, but wraps it in Tx and Rx sub-types
* Adds split() method similar to nRF for getting indepdendent TX and RX
  parts
* Implements e-h traits for TX and RX types
* Add stm32h7 example
2022-03-15 10:35:37 +01:00
Dario Nieuwenhuis
1dc618f0e4 stm32/spi: fix blocking transfer hanging after async. 2022-03-15 04:13:33 +01:00
Grant Miller
49ef19c0b2 stm32/spi: Clear rx fifo in blocking methods 2022-03-14 21:55:37 -05:00
Dario Nieuwenhuis
059b164234 stm32/spi: do not clear rxfifo in SPIv3, the hw already does it. 2022-03-15 02:37:08 +01:00
Dario Nieuwenhuis
4579192832 stm32/spi: fix hang in SPIv3 by not waiting for rxfifo empty in finish_dma. 2022-03-15 02:36:34 +01:00
Dario Nieuwenhuis
306110f56e stm32/spi: implement async trasnfer_in_place 2022-03-15 00:40:48 +01:00
Grant Miller
f1d6c95205 rustfmt 2022-03-14 18:22:41 -05:00
Grant Miller
71632648c7 Fix zero-length-slice bugs 2022-03-14 18:14:55 -05:00
Grant Miller
15c533fe2a Fix async write bug 2022-03-14 18:04:31 -05:00
Grant Miller
6e00c58854 Make all functions generic over word size 2022-03-14 16:53:50 -05:00
Grant Miller
f0b62bc8e0 Use const REGS 2022-03-14 15:56:08 -05:00
Grant Miller
482ffea4dd Finish unification 2022-03-14 15:56:08 -05:00
Grant Miller
406b1b3dd2 Finish matching versions 2022-03-14 15:56:08 -05:00
Grant Miller
7cd6f00a90 Add set_txdmaen and set_rxdmaen functions 2022-03-14 15:56:08 -05:00
Grant Miller
444b37fcdf Add flush_rx_fifo function 2022-03-14 15:56:08 -05:00